Xilinx ChipScope Pro User Manual page 88

Chapter 4: Using the ChipScope Pro Analyzer
The TX Polarity Invert setting controls the polarity of the data sent out of the TX pins of the
GTX transceiver channel. To change the polarity of the TX side of the GTX transceiver,
check the TX Polarity Invert box.
The TX Bit Error Inject button inverts the polarity of a single bit in a single transmitted
word. The receiver endpoint of the channel that is connected to this transmitter should
detect a single bit error.
The TX Diff Output Swing combo box controls the differential swing of the transmitter.
Change the value in the combo box to change the swing.
The TX Pre-Emphasis combo box controls the amount of pre-emphasis on the transmitted
signal. Change the value in the combo to change the emphasis.
The RX Polarity Invert setting controls the polarity of the data received by the RX pins of
the GTX channel. To change the polarity of the RX side of the GTX transceiver, check the
RX Polarity Invert box.
The RX AC Coupling Enabled setting controls whether the built-in AC coupling
capacitors are enabled or not.
The RX Termination Voltage setting controls which supply is used in the RX termination
network.
The RX Equalization setting controls the internal RX equalization circuit.
BERT Settings
The TX/RX Data Pattern settings are used to select the data pattern that is used by the
transmit pattern generator and receive pattern checker, respectively. These patterns
include PRBS 7, 15, 23, and 31, and Clk 2x and 10x.
The RX Bit Error Ratio field contains the currently calculated bit error ratio for the GTX
transceiver channel. It is expressed as an exponent. For instance, 1.000E-12 means that one
bit error happens (on average) for every trillion bits received.
The RX Received Bit Count field contains a running tally of the number of bits received.
This count resets when the BERT Reset button is clicked.
The RX Bit Error Count field contains a running tally of the number of bit errors detected.
This count resets when the BERT Reset button is clicked.
The BERT Reset button resets the bit error and received bit counters. It is appropriate to
reset the BERT counters after the GTX channel is linked and stable.
Clocking Settings
The TXOUTCLK Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the TXOUTCLK0 port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The TXUSRCLK Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the TXUSRCLK port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The TXUSRCLK2 Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the TXUSRCLK2 port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The RXUSRCLK Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the RXUSRCLK port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
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UG029 (v14.3) October 16, 2012