Xilinx ChipScope Pro User Manual page 22

Chapter 1: Introduction
Table 1-6: IBERT v2.0 Core for the Virtex-6 FPGA GTH Transceivers
22
Feature
Multiple GTH Transceivers
Pattern Generator
Pattern Checker
Fabric Width
BERT Parameters
Polarity
Reset
Link and Lock Status
DRP Read
DRP Write
Ports Read
Ports Write
Status
www.xilinx.com
Description
Up to sixteen transceivers can be selected per design
One pattern generator per selected GTH transceiver (four
per QUAD) is used. PRBS 7-bit, PRBS 15-bit PRBS 23-bit,
PRBS 31-bit, Clk 2x, and Clk 10x patterns are available. The
desired pattern from that set can be selected individually
for each GTH transceiver at runtime.
One pattern checker per selected GTH transceiver is used
(four per QUAD). The same pattern set is available as the
pattern generator. The pattern can be chosen for each GTH
transceiver at runtime.
The FPGA fabric interface to the GTH QUAD can be either
16- or 20-bits wide and selectable at generate time.
Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
The polarity of the TX or RX side of each GTH transceiver
can be changed at runtime.
The BER counters for each GTH transceiver can be reset
independently. A reset is also available for the entire GTH
QUAD, including PLLs.
Link, DCM, and PLL lock status are gathered for each GTH
transceiver in the core.
The DRP space for each GTH transceiver can be read
independently of all others.
The contents of the DRP for each GTH transceiver can be
changed at runtime, with single-bit granularity.
The contents of the registers that monitor the GTH
transceiver ports can be read independently of others.
The contents of the registers that control the GTH
transceiver ports can be changed at runtime.
The dynamic status information for the entire core can be
read out of the core at runtime.
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012