Xilinx ChipScope Pro User Manual page 24

Chapter 1: Introduction
Table 1-8: IBERT v2.02a Core for the 7 Series FPGA GTX Transceivers
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Feature
Multiple GTX Transceivers
Pattern Generator
Pattern Checker
Fabric Width
Polarity
Reset
Link and Lock Status
DRP Read
DRP Write
Ports Read
Ports Write
Status
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Description
Up to fifteen transceivers can be selected per design.
One pattern generator per selected GTX transceiver is used.
PRBS 7-bit, PRBS 15-bit PRBS 23-bit, PRBS 31-bit, Clk 2x, and
Clk 10x patterns are available. The desired pattern from that
set can be selected individually for each GTX transceiver at
runtime.
One pattern checker per selected GTX transceiver is used.
The same pattern set is available as the pattern generator. The
pattern can be chosen for each GTX transceiver at runtime.
The FPGA fabric interface to the GTX transceiver can be
either 32- or 40-bits wide and selectable at generate time.
The polarity of the TX side of each GTX transceiver can be
changed at runtime.
Each GTX transceiver can be reset independently. A reset is
also available to reset the entire MGT, including PLLs and
CPLLs.
Link, and CPLL/QPLL lock status are gathered for each GTX
transceiver in the core.
The contents of the DRP space for each GTX transceiver can
be read independently of all others.
The contents of the DRP for each GTX transceiver can be
changed at runtime, with single-bit granularity.
The contents of the registers that monitor the GTX transceiver
ports can be read independently of others.
The contents of the registers that control the GTX
transceiver's ports can be changed at runtime.
The dynamic status information for the entire core can be
read out of the core at runtime.
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012