Xilinx ChipScope Pro User Manual page 83

The RX Polarity Invert setting controls the polarity of the data received by the RX pins of
the GTX channel. To change the polarity of the RX side of the GTX transceiver, check the
RX Polarity Invert box.
The RX AC Coupling Enabled setting controls whether the built-in AC coupling
capacitors are enabled or not.
The RX Termination Voltage setting controls which supply is used in the RX termination
network.
The RX Equalization setting controls the internal RX equalization circuit.
BERT Settings
The TX Data Pattern and RX Data Pattern settings are used to select the data pattern that
is used by the transmit pattern generator and receive pattern checker, respectively. These
patterns include PRBS 7, 15, 23, and 31, and Clk 2x and 10x.
The RX Bit Error Ratio field contains the currently calculated bit error ratio for the GTX
transceiver channel. It is expressed as an exponent. For instance, 1.000E-12 means that one
bit error happens (on average) for every trillion bits received.
The RX Received Bit Count field contains a running tally of the number of bits received.
This count resets when the BERT Reset button is clicked.
The RX Bit Error Count field contains a running tally of the number of bit errors detected.
This count resets when the BERT Reset button is clicked.
The BERT Reset button resets the bit error and received bit counters. It is appropriate to
reset the BERT counters after the GTX channel is linked and stable.
Clocking Settings
The TX DCM Reset button resets the DCM that uses the TXOUTCLK output to generate
the TXUSRCLK and TXUSRCLK2 clocks.
The RX DCM Reset button resets the DCM that controls uses the RXRECCLK output to
generate the RXUSRCLK and RXUSRCLK2 clocks.
The TXUSRCLK Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the TXUSRCLK port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The TXUSRCLK2 Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the TXUSRCLK2 port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The RXUSRCLK Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the RXUSRCLK port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
The RXUSRCLK2 Freq (MHz) indicator shows the approximate clocking frequency (in
MHz) of the RXUSRCLK2 port of the GTX transceiver. The accuracy of this status indicator
depends on the frequency of the system clock that was specified at compile-time.
DRP Settings Panel
The DRP Settings panel contains a table that is made up of one or more vertical columns
and horizontal rows. Each column represents a specific active GTX transceiver. Each row
represents a specific DRP attribute or address.
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
www.xilinx.com
ChipScope Pro Analyzer Features
83