Xilinx ChipScope Pro User Manual page 23

Table 1-7: IBERT v2.0 Core for the Spartan-6 FPGA GTP Transceivers
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Feature
Multiple GTP Transceivers
Pattern Generator
Pattern Checker
Fabric Width
BERT Parameters
Polarity
Reset
Link and Lock Status
DRP Read
DRP Write
Ports Read
Ports Write
Status
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ChipScope Pro Cores Description
Description
Up to eight transceivers can be selected per design.
One pattern generator per selected GTP transceiver (two
per DUAL) is used. PRBS 7-bit, PRBS 15-bit PRBS 23-bit,
PRBS 31-bit, Clk 2x, and Clk 10x patterns are available. The
desired pattern from that set can be selected individually
for each GTP transceiver at runtime.
One pattern checker per selected GTP transceiver is used
(two per DUAL). The same pattern set is available as the
pattern generator. The pattern can be chosen for each GTP
transceiver at runtime.
The FPGA fabric interface to the GTP transceiver is 20 bits.
Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
The polarity of the TX or RX side of each GTP transceiver
can be changed at runtime.
Each GTP transceiver and its BER counters can be reset
independently. A reset is also available to reset the entire
GTP transceiver, including PLLs.
Link, DCM, and PLL lock status are gathered for each GTP
transceiver in the core.
The contents of the DRP space for each GTP transceiver can
be read independently of all others.
The contents of DRP for each GTP transceiver can be
changed at runtime, with single-bit granularity.
The contents of the registers that monitor the GTP
transceiver ports can be read independently of others.
The contents of the registers that control the GTP
transceiver ports can be changed at runtime.
The dynamic status information for the entire core can be
read out of the core at runtime.
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