Xilinx ChipScope Pro User Manual page 21

Table 1-5: IBERT v2.0 Core for the Virtex-6 FPGA GTX Transceivers
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Feature
Multiple GTX
Transceivers
Pattern Generator
Pattern Checker
Fabric Width
BERT Parameters
Polarity
Reset
Link and Lock Status
DRP Read
DRP Write
Ports Read
Ports Write
Status
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Description
Up to eight transceivers can be selected per design.
One pattern generator per selected GTX transceiver is used.
PRBS 7-bit, PRBS 15-bit PRBS 23-bit, PRBS 31-bit, Clk 2x, and Clk
10x patterns are available. The desired pattern from that set can
be selected individually for each GTX transceiver at runtime.
One pattern checker per selected GTX transceiver is used. The
same pattern set is available as the pattern generator. The pattern
can be chosen for each GTX transceiver at runtime.
The FPGA fabric interface to the GTX transceiver can be either
16- or 20-bits wide and selectable at generate time.
Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
The polarity of the TX or RX side of each GTX transceiver can be
changed at runtime.
Each GTX transceiver and its BER counters can be reset
independently. A reset is also available to reset the entire MGT,
including PLLs.
Link, DCM, and PLL lock status are gathered for each GTX
transceiver in the core.
The contents of the DRP space for each GTX transceiver can be
read independently of all others.
The contents of the DRP for each GTX transceiver can be
changed at runtime, with single-bit granularity.
The contents of the registers that monitor the GTX transceiver
ports can be read independently of others.
The contents of the registers that control the GTX transceiver's
ports can be changed at runtime.
The dynamic status information for the entire core can be read
out of the core at runtime.
ChipScope Pro Cores Description
21