Xilinx ChipScope Pro User Manual page 44

Chapter 3: Using the ChipScope Pro Core Inserter
Entering the Data Width
The width of each data sample word stored by the ILA core is called the data width. If the
data and trigger words are independent from each other, then the maximum allowable
data width depends on the target device type and data depth. However, regardless of these
factors, the maximum allowable data width is 4,096 bits (or 256 bits for Spartan-3,
Spartan-3E, Spartan-3A, Spartan-3A DSP, and Virtex-4 devices).
Selecting the Data Type
The data captured by the ILA trigger port is controlled by the Data Same as Trigger
checkbox and can come from two source types:
•
•
Selecting the Data-Same-As-Trigger Ports
If the Data Same As Trigger checkbox is selected, then a checkbox for each TRIGn port
appears in the data options screen. Use these checkboxes to select the individual trigger
ports to be included in the aggregate data port. A maximum data width of 4,096 bits (or 256
bits for Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, and Virtex-4 devices) applies
to the aggregate selection of trigger ports.
Choosing ATC2 Data Capture Settings
If you are inserting an ATC2 core, the following sections describe the ATC2 data capture
settings.
Capture Mode
The Capture Mode setting of the ATC2 core can be set to either STATE mode for
synchronous data capture to the CLK input signal or to TIMING mode for asynchronous
data capture. In STATE mode, the data path through the ATC2 core uses pipeline flip-flops
that are clocked on the CLK input port signal. In TIMING mode, the data path through the
ATC2 core is composed purely of combinational logic all the way to the output pins. Also,
in TIMING mode, the ATCK pin is used as an extra data pin.
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Data Same as Trigger (checked ON)
−
You can use the signals connected to the trigger ports for triggering and for data
capture. This mode is very common in most logic analyzers because you can
capture and collect any data that is used to trigger the core.
−
Individual trigger ports can be selected to be included in the data port. If this
selection is made, then the DATA input port is not included in the port map of the
ILA core.
−
This mode conserves CLB and routing resources in the ILA core, but is limited to
a maximum aggregate data sample word width of 4,096 bits (or 256 bits for
Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, and Virtex-4 devices).
Data Separate from Trigger (checked OFF)
−
The data port is completely independent of the trigger ports
−
This mode is useful when you want to limit the amount of data being captured
−
In the case of data not same as trigger, the Data Port Width parameter must be
specified.
www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012