Analog-To-Digital Converters - Analog Devices ADAU1961 Manual

Digital Microphone Input
When using a digital microphone connected to the JACKDET/
MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)
must be set to 10 to enable the microphone input and disable
the jack detection function. The ADAU1961 must operate in
master mode and source BCLK to the input clock of the digital
microphone.
The digital microphone signal bypasses record path mixers and
ADCs and is routed directly into the decimation filters. The
digital microphone and ADCs share decimation filters and,
therefore, both cannot be used simultaneously. The digital
microphone input select bit, INSEL, can be set in Register R19
(ADC control register, Address 0x4019). Figure 35 depicts the
digital microphone interface and signal routing.
TO JACK
DETECTION
CIRCUIT
RIGHT
ADC
LEFT
ADC
Figure 35. Digital Microphone Interface Block Diagram
Microphone Bias
The MICBIAS pin provides a voltage reference for electret analog
microphones. The MICBIAS voltage is set in Register R10
(record microphone bias control register, Address 0x4010). In
this register, the MICBIAS output can be enabled or disabled.
Additional options include high performance operation and a
gain boost. The gain boost provides two different voltage biases:
0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-
mance bit increases supply current to the microphone bias
circuit to decrease rms input noise.
The MICBIAS pin can also be used to cleanly supply voltage
to digital microphones or analog microphones with separate
power supply pins.
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JACKDET/MICIN
R2: DIGITAL MICROPHONE/
JACK DETECTION
CONTROL
JDFUNC[1:0]
DIGITAL MICROPHONE
INTERFACE
LEFT RIGHT
CHANNEL CHANNEL
R19: ADC CONTROL
INSEL
DECIMATORS

ANALOG-TO-DIGITAL CONVERTERS

The ADAU1961 uses two 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with selectable oversampling ratios of 64× or
128× (selected by Bit 3 in Register R17, Address 0x4017).
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) is 1.0 V rms with
AVDD = 3.3 V. This full-scale analog input will output a digital
signal at −1.38 dBFS. This gain offset is built into the ADAU1961
to prevent clipping. The full-scale input level scales linearly with
the level of AVDD.
For single-ended and pseudo-differential signals, the full-scale
value corresponds to the signal level at the pins, 0 dBFS.
The full differential full-scale input level is measured after the
differential amplifier, which corresponds to −6 dBFS at each pin.
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
The digital ADC volume can be attenuated using Register R20 (left
input digital volume register, Address 0x401A) and Register R21
(right input digital volume register, Address 0x401B).
High-Pass Filter
By default, a high-pass filter is used in the ADC path to remove
dc offsets; this filter can be enabled or disabled in Register R19
(ADC control register, Address 0x4019). At f
corner frequency of this high-pass filter is 2 Hz.
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ADAU1961
= 48 kHz, the
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