Analog Devices ADAU1961 Manual page 45

Stereo, low power, 96 khz, 24-bit audio codec with integrated pll
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Byte
Bits
4
[6:3]
4
[2:1]
4
0
5
1
5
0
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Bit Name
Description
R[3:0]
PLL integer setting.
Setting
0010
0011
0100
0101
0110
0111
1000
X[1:0]
PLL input clock divider.
Setting
00
01
10
11
Type
Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
Lock
PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
PLLEN
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.
Value of R
2 (default)
3
4
5
6
7
8
Value of X
1 (default)
2
3
4
Rev. 0 | Page 45 of 76
ADAU1961

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