Analog Devices ADAU1961 Manual page 57

R19: ADC Control, 16,409 (0x4019)
Bit 7
Reserved
Table 44. ADC Control Register
Bits Bit Name
6 ADCPOL
5 HPF
4 DMPOL
3 DMSW
2 INSEL
[1:0] ADCEN[1:0]
R20: Left Input Digital Volume, 16,410 (0x401A)
Bit 7
Table 45. Left Input Digital Volume Register
Bits Bit Name
[7:0] LADVOL[7:0]
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Bit 6 Bit 5
ADCPOL HPF
Description
Invert input polarity.
0 = normal (default).
1 = inverted.
ADC high-pass filter select. At 48 kHz, f
0 = off (default).
1 = on.
Digital microphone data polarity swap.
0 = invert polarity.
1 = normal (default).
Digital microphone channel swap. Normal operation sends the left channel on the rising edge of the clock and
the right channel on the falling edge of the clock.
0 = normal (default).
1 = swap left and right channels.
Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × f
ADC_SDATA is expected to have left and right channels interleaved.
0 = digital microphone inputs off, ADCs enabled (default).
1 = digital microphone inputs enabled, ADCs off.
ADC enable.
Setting
00
01
10
11
Bit 6 Bit 5
Description
Controls the digital volume attenuation for left channel inputs from either the left ADC or the left digital micro-
phone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 71 for a complete
list of the volume settings.
Setting
00000000
00000001
00000010
...
11111110
11111111
Bit 4 Bit 3
DMPOL DMSW
= 2 Hz.
3dB
ADCs Enabled
Both off (default)
Left on
Right on
Both on
Bit 4 Bit 3
LADVOL[7:0]
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
...
−95.25 dB
−95.625 dB
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Bit 2 Bit 1
INSEL
ADCEN[1:0]
Bit 2 Bit 1
ADAU1961
Bit 0
, and
S
Bit 0