R42: Jack Detect Pin Control, 16,433 (0x4031)
With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to
a defined state when the signal source becomes three-state.
Bit 7
Reserved
Table 67. Jack Detect Pin Control Register
Bits
Bit Name
5
JDSTR
[3:2]
JDP[1:0]
R67: Dejitter Control, 16,438 (0x4036)
The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated or
bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling
and reenabling certain subsystems in the device—that is, the ADCs, serial ports, and DACs—during operation can cause the associated
dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports
are in slave mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output
to the next subsystem in the device. Any time that audio must pass through the ADCs, serial port, or DACs, the dejitter circuit can be
bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately reactivated, without a wait
period, by setting the dejitter window size to the default value of 3.
Bit 7
Table 68. Dejitter Control Register
Bits
Bit Name
[7:0]
DEJIT[7:0]
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Bit 6
Bit 5
JDSTR
Description
JACKDET/MICIN pin drive strength.
0 = low (default).
1 = high.
JACKDET/MICIN pad pull-up/pull-down configuration.
Setting
00
01
10
11
Bit 6
Bit 5
Description
Dejitter window size.
Window Size
00000000
...
00000011
...
00000101
Bit 4
Bit 3
Reserved
JDP[1:0]
Configuration
Pull-up
Reserved
None (default)
Pull-down
Bit 4
Bit 3
DEJIT[7:0]
Core Clock Cycles
0
...
3 (default)
...
5
Rev. 0 | Page 69 of 76
Bit 2
Bit 1
Reserved
Bit 2
Bit 1
ADAU1961
Bit 0
Bit 0
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