Analog Devices ADAU1961 Manual page 56

ADAU1961
R17: Converter Control 0, 16,407 (0x4017)
Bit 7 Bit 6
Reserved
Table 42. Converter Control 0 Register
Bits Bit Name
[6:5] DAPAIR[1:0]
4 DAOSR
3 ADOSR
[2:0] CONVSR[2:0]
R18: Converter Control 1, 16,408 (0x4018)
Bit 7 Bit 6
Table 43. Converter Control 1 Register
Bits Bit Name
[1:0] ADPAIR[1:0]
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Bit 5 Bit 4
DAOSR
DAPAIR[1:0]
Description
On-chip DAC serial data selection in TDM mode.
Setting
00
01
10
11
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, f
of the core clock. The serial port mirrors the converter sampling rates set in this register.
Setting
000
001
010
011
100
101
110
111
Bit 5 Bit 4
Reserved
Description
On-chip ADC serial data selection in TDM mode.
Setting
00
01
10
11
Bit 3 Bit 2
ADOSR
Pair
First pair (default)
Second pair
Third pair
Fourth pair
. The base sampling rate is determined by the operating frequency
S
Sampling Rate
f
S
f /6
S
f /4
S
f /3
S
f /2
S
f /1.5
S
f /0.5
S
Reserved
Bit 3 Bit 2
Pair
First pair (default)
Second pair
Third pair
Fourth pair
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Bit 1
CONVSR[2:0]
Base Sampling Rate (f = 48 kHz)
S
48 kHz, base (default)
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Bit 1
ADPAIR[1:0]
Bit 0
Bit 0