Analog Devices ADAU1961 Manual page 26

ADAU1961
Table 15. Fractional PLL Parameter Settings for f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 16. Fractional PLL Parameter Settings for f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 17. Integer PLL Parameter Settings for f
MCLK Input (MHz)
12.288
24.576
1
X = don't care.
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= 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × f
S
Input Divider (X) Integer (R)
1 5
1 3
1 3
2 6
2 4
2 4
2 4
2 3
2 3
2 3
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
S
Input Divider (X) Integer (R)
1 6
1 4
1 3
2 6
2 5
2 4
2 4
2 4
2 3
2 3
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
S
Input Divider (X) Integer (R)
1 4
1 2
Denominator (M) Numerator (N)
625 403
625 477
8125 3849
125 34
125 88
1025 604
1375 772
625 477
8125 3849
1875 647
Denominator (M) Numerator (N)
125 18
125 12
1625 1269
75 62
25 3
205 204
825 796
125 12
1625 1269
1125 721
Denominator (M) Numerator (N)
Don't care Don't care
Don't care Don't care
Rev. 0 | Page 26 of 76
)
S
R2: PLL Control Setting (Hex)
0x0271 0193 2901
0x0271 01DD 1901
0x1FBD 0F09 1901
0x007D 0022 3301
0x007D 0058 2301
0x0401 025C 2301
0x055F 0304 2301
0x0271 01DD 1B01
0x1FBD 0F09 1B01
0x0753 0287 1B01
)
S
R2: PLL Control Setting (Hex)
0x007D 0012 3101
0x007D 000C 2101
0x0659 04F5 1901
0x004B 003E 3301
0x0019 0003 2B01
0x00CD 00CC 2301
0x0339 031C 2301
0x007D 000C 2301
0x0659 04F5 1B01
0x0465 02D1 1B01
)
S
R2: PLL Control Setting (Hex)
0xXXXX XXXX 2001
0xXXXX XXXX 1001
1