Analog Devices ADAU1961 Manual page 41

LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
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LEFT CHANNEL
MSB
Figure 57. I
LEFT CHANNEL
MSB
Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel
LEFT CHANNEL
MSB
Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
BCLK
32 BCLKs
SDATA
SLOT 0
MSB TDM
CH
0
SLOT 0
32 BCLKs
MSB
LSB
f
1/
S
2
S Mode—16 Bits to 24 Bits per Channel
LSB MSB
f
1/
S
LSB
f
1/
S
128 BCLKs
SLOT 1
SLOT 2
LRCLK
BCLK
SDATA
MSB MSB – 1 MSB – 2
Figure 60. TDM 4 Mode
SLOT 1 SLOT 2
Figure 61. TDM 4 Mode with Pulse Word Clock
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RIGHT CHANNEL
LSB
RIGHT CHANNEL
LSB
RIGHT CHANNEL
MSB
SLOT 3
SLOT 3
ADAU1961
LSB