Agilent Technologies PSG Series Service Manual page 90

A9 YIG Driver A26 Micro Interface Deck
DBL20_AMP_ON_H
V_GHZ_DAC FM_FREQ_COMP_L
FM_GAIN_DAC FM_FREQ_COMP
DBL20_PATH
VSWP_DAC FM_FREQ_COMP_H
6
FM_ATTEN FM
Coil
A29 20 GHz Doubler
FM_ATTEN_L 230: :1k
800k
: :
:
> 3.2 GHz to
FM_ATTEN_H :4k YIG
10 GHz
3-10
230 > + 13 dBM 3-10
2k +32 V
PRETUNE_DAC 5-10
Main
Coil
X2
HOLD_DAC
Doubler
COMP_DAC
Pretune
Speedup 3-10
H_SPEEDUP_EN
J4 to A5 Sampler J3
A6 Frac-N YTO_FM from 3.2 - 10 GHz 3.2 - 10 GHz
LYO Loop Hold 1
> -7 dBm > -7 dBm
YTO_FM A6 Frac-N
A6 Frac-N (Fine Tune)
To A8 Pre Level Drive
8.5 GHz
Multi Modulus
To A8
Divider
¸ 2 / 4 / 8 / 1 6
RF
6 6 Power
Detector
DIVIDER_CONTROL To
LPF_SELECT Analog Bus
RF Out
A8 Output
H_BYPASS Bypass Mode
HET_SELECT_L
Prelevel
Prelevel Detector
Drive
MOD_DRIVER_
PRE_
LEVEL_ BIAS/GAIN_DAC
250 MHz
REF_DAC Gain 1200
to 4 GHz
Adj. ALC MHz 6 dB
ALC
Mod Pulse
MOD_
850 to
GAIN_ADJUST_DAC OFFSET_DAC
1150
MHz
OUTPUT_LP_FILTER_SELECT MODLIN_DAC
ALC_MOD_OFFSET_DAC
ALC_MOD_DRIVER_
BIAS/GAIN_DAC
1 GHz
se990a
A30 Modulator Filter
MODF_PATH
10-20
3-10 6
MODF_AMP_ON_H
750 MHz
5-8
3-20
J2
10-13
Limiter >3.2 - 20 GHz 13-20
10-20
ALC
> 14 dBm
Pulse
MODF_PLS_ENB_L
16-20
8-13
13-16 3.2
3-5
J3 250 kHz - 3.2 GHz
A23 Low Band
Coupler / Detecter
A10 ALC
0-2 GHz
HIPWRCAL_DAC
LOG_BRKPT_DAC
DET_OFS_DAC
Hiband
Detector
Dual Slope Log Amp
Loband 0
Detector
1 1 kHz
External 2
Detector
H_DET_LPF
DETECTOR_SEL
L_DETLVLX25
H_DEEP_AM
0-3 GHz
400
MHz
L_Open Loop
0-3.2 GHz
L ALC Hold
L ALC Hold
BB_FILTERED
L Pulsed RF Off
Burst
BB_THRU
Comp
_
H_BYPASS
+
AM Input
MOD_L_BW
Log
L_RF_OFF_MOD
3 dB
L_EN_LIN/LOG
L_MODE
H_EXP_AM
L_HOLD_ALC
H_LIN_AM
Ref
From A7 Reference
DBL40_LPF
ATTEN
DBL40_BIAS
DBL40_PATH
5
2
3 DBL40_AMP
A24 Coupler
A27 40 GHz Doubler A25 Detector
2-20 or 2-40 GHz
AT1
J4
20-26 20-40
Attenuator
10-20 GHz GHz
> 20 dBm X2 J2
Option 1EA
Doubler 250 kHz - 3.2 GHz > 17 dBm 5/10/40/20/40
J1 32-40 30 or 40
> 25 dBm > 3.2 - 20 GHz > 15.5 dBm
0-20 > 20 GHz > 13 dBm
Optional
Option 1EA
GHz Attenuator
26-32
250 kHz - 3.2 GHz > 17 dBm
> 3.2-20 GHz > 20.5 dBm
J3
> 20 GHz > 18 dBm
J2 250 kHz - 3.2 GHz > 18 dBm
> 3.2 GHz - 20 GHz > 18 dBm, Option 1EA > 23 dBm
> 21 dBm
FM_OFF_H SOURCE_SETTLED_H
+V
6.8 volts
SM Input
ALCMOD_LIN_DAC
L_OPENLOOP
H_RF_OFF ALCMOD_BIAS_DAC
ALC_BW_SEL
L_ALC_HOLD_LATCHED Cx1000 L Unlvl
1 Interrupt
H_SM_MODE Cx100
2
+
_
Cx10
+66mV/dB
3
Det level L_20/
_
all open = 0
H_40DIG
C +
Open = Exponential
Modulation Driver
Hold
Int Out
_
+10dB/V
x 25 S
+
+V
ALCMODGAIN_DAC
ALC
L_20MOD
FeedFwd H_BELOW_3.2GHZ
_OFF
3.2 to 20 GHz
ALC Mod
Loband ALC Mod
-10v
+
_
Deep
AM
Comp ADC
ADC
MUX
I/H
Delay
ALC Ref
-66mV/dBm
S
Delay
LVL_DAC
S
H_BURST
RF
Out
A11 Pulse / Analog Modulation Generator
A bus
EXT1_PEAK_V EXT1_AC_H
EXT1_50_ Peak
REF_DAC Ext1_High_H
OHMS_H
Detect
-10Vref
Ext 1, Ext1_low_H
Front X2
Panel Rin = 600
or 50 ohms
EXT1_PEAK_V
A bus
REF_DAC
Peak EXT2_AC_H
EXT2_50_ Ext2_High_H
OHMS_H Detect
-10Vref
Ext 2, Ext2_low_H
Front X2
Rin = 600
Panel
or 50 ohms
IPGCLK Out
of Lock L
ABUS
IPGCLK_ON_H
IPGCLK
TUNE
10 MHz 100 MHZ IPG
IPG_CLK A Bus
Clock Latch DAC
12 12
NSCLK Out -
Data Data S
of Lock L
ABUS
NSCLK
NSCLK_ON_H -
TUNE Clock Clock
10 MHz "Elsie" NS
Digital 10 MHz 33.554 MHz FGEN1_OFFSET_
OCA
DAC
NS Clock NS_CLK
ODBUS
OCC FGEN2_OFFSET_
DAC
CNTOUT
Clock Clock
NS_Reset -
12 12
-
Data
NS_Address Data S
NS_Data A Bus
Latch DAC
FM1_MUX
FM_OFFSET1
A Bus
_DAC
-
+
FM
S
+
-
FM_OFFSET2
_DAC
FM2_SCALE_DAC
FM2_MUX
FM
MOD_MUX
Gate / Pulse /
Trigger Input,
Front Panel
A Bus
Internal Pulse Generator
L Pulsed
Vref
PULSE_OUT_SEL RF Off
A Bus
FED_VREF_DAC
FED_PULSE_SEL
PULSE IN SEL
RED_PULSE_SEL
RED_VREF_DAC
A Bus
PULSE_ED_SEL
PG_MODE
PG_TRIGGER_INVERT
PG_PULSE_REP_INTERVAL
VIDEO_OUT_EN_L A Bus
PG_PULSE_REP_INTERVAL
Video Out
PG_VIDEO_BEGIN 50 ohm
PG_VIDEO_END
PG_SYNC_BEGIN
SYNC_OUT_EN_L
A Bus
PG_SYNC_END
Sync Out
50 ohm
AM1_MUX
AM1_DAC
External 1
A Bus
External 2
+
AM_OFFSET
Audio 1 _DAC
- S AM
Audio 2
F_GEN1
+
F_GEN2
AM2_DAC
AM2_MUX
AM
LF_OUT_DAC
LFO
A Bus
Front Panel
50 ohm
Block Diagram for the RF Path