Standard Event Status Enable Register - Agilent Technologies Agilent E5250A User Manual

Agilent technologies low leakage switch mainframe user's guide
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Table 7-2
Command Reference

Standard Event Status Enable Register

Standard Event Status Register of E5250A
Bit
Definition
0
Operation Complete
(OPC)
1
Not Used
2
Query Error (QYE)
3
Device Dependent
Error (DDE)
4
Execution Error (EXE)
5
Command Error
(CME)
6
Not Used
7
Power On (PON)
8 to 15
Not used
Standard Event Status Enable Register
The Standard Event Status "Enable" Register is an 8-bit register that can be used by
the programmer to select which bits of Standard Event Status Register are enabled.
The status of the enabled bits are ORed together, and result of OR will be reported to
the ESB bit (Bit5) of the Status Byte Register.
The 8 bits of this register correspond to the 8 bits of the Standard Event Status
Register. Refer to Figure 7-4.
7-54
Explanation
This event bit has meaning only if a request
to monitor is set by the *OPC command.
Refer to "*OPC" on page 7-9. This bit is set
to 1 if there are no pending operations.
Always 0.
An attempt is being made to read data
from the Output Queue when no data is
present or pending.
Data in the Output Queue has been lost.
This event bit indicates that an error has
occurred which is not a Command Error, a
Query Error, or an Execution Error.
Syntax of command is correct, but cannot be
executed due to some condition of the
E5250A.
A command syntax error has been detected.
Always 0.
This event bit indicates that an off-to-on
transition has occurred in instrument's
power supply.
Always 0.
Agilent E5250A User's Guide, Edition 11

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