Figure A.4. Fpga - Lattice Semiconductor MachXO2 Breakout Board User Manual

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MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
5
VCCIO3
MAKE PWR TRACES
CAPABLE OF 1A
J4
2
4
6
PL2B_L_GPPLC_FB
PL2D_L_GPLLC_IN
8
PL3B_PCLKC3_2
10
PL3D
12
14
PL4B
16
PL4D
18
20
PL5B_PCLKC3_1
22
PL5D
24
26
PL8B
28
PL8D
30
32
PL9B_PCLKC3_0
34
36
PL10B
38
PL10D
40
Header2x20
DNI
+3.3V
PL10A
This is optional
R54
to enable or
disable the
0
crystal.
DNI
X2
1
EN
Vcc
2
GND
Output
CB3LV-3C-50M0000
50MHz OSC
Note:
1. The Pin Functions indicated in the schematic symbol U3 are for LCMXO2-1200ZE-1TG144C. For the Pin
Functions of the board with LCMXO2-7000HE-4TG144C, refer to the pinout file.
2. In the version of the board with LCMXO2-7000HE-4TG144C, the net name "VCCIO3" is also connected to Pin 7
(VCCIO5), and Pin 16 (VCCIO4).
3. Pin 7 of the version of the board with LCMXO2-7000HE-4TG144C, is VCCIO5.
4. Pin 16 of the version of the board with LCMXO2-7000HE-4TG144C, is VCCIO4.
5
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
4
VCC_3.3V
C25
C26
0.1uF
0.1uF
PL2A_L_GPLLT_FB
1
PL2B_L_GPPLC_FB
2
3
PL2C_L_GPLLT_IN
4
PL2D_L_GPLLC_IN
1
3
5
PL3A_PCLKT3_2
5
6
PL2A_L_GPLLT_FB
PL3B_PCLKC3_2
7
PL2C_L_GPLLT_IN
PL3C
9
9
PL3A_PCLKT3_2
PL3D
10
11
PL3C
13
PL4A
11
15
PL4A
PL4B
12
17
PL4C
PL4C
13
19
PL4D
14
21
PL5A_PCLKT3_1
15
23
PL5C
17
25
27
PL8A
PL5A_PCLKT3_1
19
29
PL8C
PL5B_PCLKC3_1
20
31
PL5C
21
33
PL9A_PCLKT3_0
PL5D
22
35
37
PL10A
PL8A
23
39
PL10C
PL8B
24
PL8C
25
PL8D
26
PL9A_PCLKT3_0
27
PL9B_PCLKC3_0
28
31
PL10A
32
PL10B
33
PL10C
34
PL10D
35
VCCIO3
2
VCCIO3
7
16
C27
30
C28
C29
C30
R27
1
0.01uF
0.1uF
0.1uF
0.1uF
+3.3V
CSSPIN_PB4C
C53
0.1uF
4
MCLK_CCLK_PB6C
3
PL9A_PCLKT3_0
S0_SPISO_PB6D
PCLKT2_0_PB9A
PCLKC2_0_PB9B
PCLKT2_PB11A
PCLKC2_PB11B
4
3
U3-3
1
BANK 3
BANK 2
38
PB4A
PL2A/L_GPLLT_FB
PB4A
39
PB4B
PL2B/L_GPPLC_FB
PB4B
40
CSSPIN_PB4C
PL2C/L_GPLLT_IN
CSSPIN/PB4C
41
PB4D
PL2D/L_GPLLC_IN
PB4D
42
PB6A
PL3A/PCLKT3_2
PB6A
43
PB6B
PL3B/PCLKC3_2
PB6B
44
MCLK_CCLK_PB6C
PL3C
MCLK/CCLK/PB6C
45
S0_SPISO_PB6D
PL3D
SO/SPISO/PB6D
47
PB9C
PL4A
PB9C
48
PB9D
PL4B
PB9D
49
PCLKT2_0_PB9A
PL4C
PCLKT2_0/PB9A
50
PCLKC2_0_PB9B
PL4D
PCLKC2_0/PB9B
NC0
52
PB11C
NC1
PB11C
54
PB11D
PB11D
55
PCLKT2_PB11A
PL5A/PCLKT3_1
PCLKT2_1/PB11A
56
PCLKC2_PB11B
PL5B/PCLKC3_1
PCLKC2_1/PB11B
PL5C
57
PB15A
PL5D
PB15A
58
PB15B
PB15B
59
PB15C
PL8A
PB15C
60
PB15D
PL8B
PB15D
PL8C
61
PB18A
PL8D
PB18A
62
PB18B
PB18B
63
PL9A/PCLKT3_0
NC3
65
PB18C
PL9B/PCLKC3_0
PB18C
67
PB18D
NC2
PB18D
68
PB20A
PL10A
PB20A
69
PB20B
PL10B
PB20B
70
SN_PB20C
PL10C
SN/PB20C
71
SI_SISPI_PB20D
PL10D
SI/SISPI/PB20D
37
VCCIO3
3
VCCIO2
51
C31
VCCIO3
4
VCCIO2
66
C32
C33
VCCIO3
VCCIO2
LCMXO2-1200ZE-1TG144C
0.01uF
0.1uF
0.1uF
NOTE
PLACE ALL 100 OHM
DIFF TERM RESISTORS
ON BOTTOM OF BOARD
PB4A
R28
DNI
PB15A
R29
DNI
100
PB4B
PB15B
R30
DNI
100
PB15C
R31
DNI
PB4D
PB15D
PB6A
R32
DNI
100
PB18A
R33
DNI
PB6B
PB18B
R34
DNI
100
PB18C
R35
DNI
PB18D
PB9C
R36
DNI
100
PB20A
R37
DNI
PB9D
PB20B
100
SN_PB20C
R38
DNI
R39
DNI
SI_SISPI_PB20D
100
PB11C
R40
DNI
PB11D
R41
DNI
100
3

Figure A.4. FPGA

2
1
VCCIO2
MAKE PWR TRACES
CAPABLE OF 1A
J5
2
1
4
3
PB20B
SI_SISPI_PB20D
6
5
PB20A
8
7
PB18B
PB18A
10
9
12
11
PB15B
14
13
PB15A
16
15
18
17
PB11D
20
19
PCLKC2_PB11B
PB11C
22
21
PCLKT2_PB11A
24
23
PB9D
26
25
PCLKC2_0_PB9B
PB9C
28
27
PCLKT2_0_PB9A
30
29
PB6B
32
31
S0_SPISO_PB6D
PB6A
34
33
MCLK_CCLK_PB6C
36
35
PB4B
38
37
PB4A
40
39
CSSPIN_PB4C
Header2x20
DNI
VCCIO2
+3.3V
VCCIO2
C34
R26
1
0.1uF
100
100
100
100
100
100
AXELSY
AXELSY
AXELSYS
S S
i i T T T it t t l l l e e e
Lattice MachXO2 1200ZE Breakout Board – FPGA
i i S S S iz z z e e e
Document Number
B B B
L L L CMX X
C C
M M XO O O 2 2 2 - - - 1 1 1 200ZE E
200ZE- - - B B B - - - E E E V V V N N N
200Z
D D D at t t e e e : : :
a a
Thursday, April 21, 2011
S S S h h h e e e e e e t t t
2
1
SN_PB20C
PB18D
PB18C
PB15D
PB15C
PB4D
4 4 4
f f o o o f
5 5 5
FPGA-EB-02051-2.3

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