Figure A.2. Ice40Up5K Fpga A - Display - Lattice Semiconductor iCE40 UltraPlus User Manual

5
VCC_iCE_A
Note: C1 C2 C3
Place close 10n 0.1u 1u
to DUT
VCCPLL_A
VPP2V5_A
D
VCCIO0_iCE_A
C4 C5 C6
Note:
Place close 1u 0.1u 10n
to DUT
UART_RX_A
UART_TX_A
OSC_CLK_A
proc_cs_A
SPARE_A0
SPARE_A1
SPARE_A2
C
Note:
Place close
to DUT
VCCPLL_IN_A C7 C8
VCCPLL_A
10u 0.1u
100
R1
VCC Sense Resistors - 1 Ohm 0603
Add test points on both sides
VCC1V2 VCC2V5
B
VCC3V3 VCC1V2 VCC_iCE_A
VCC3V3 R178 1
R179 1
R180 1
R181 1
R182 1
R183 1
TP1
TP50
TP2
TP3
TP51
TP52
J17
CRSTb_A
1 2
SPARE_A2 3 4
A
5 6
CDONE_A 7 8 CDONE
CRSTb_A
9 10
iCEA Control
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02007-1.1
4
U1
C2 D2
VCC SPI_VCCIO1
B2 C1
VCCPLL IOB_35B_SPI_SS
D1
IOB_34A_SPI_SCK
E1
IOB_33B_SPI_SI
D4 F1
VPP_2V5 IOB_32A_SPI_SO
F3
CRESET_B
C3
IOB_10A
B1
IOB_24A
F2
IOB_25B_G3
D3
IOB_12A_G4_CDONE
E3
IOB_13B
F4
IOB_11B_G5
A3
VCCIO_0
A2
IOT_37A
A1
IOT_36B
B3 C4
IOT_46B_G0 VCCIO_2
A4
IOT_47A
E4
IOB_9B
A5 D5
RGB2 IOB_2A
B5 F5
RGB1 IOB_3B_G6
C5 E5
RGB0 IOB_0A
iCE5UP5K-WLCSP30
VCCPLL_IN_A SPIVCCIO1_iCE_A
VCCIO0_iCE_A VCCIO2_iCE_A
VPP2V5_A
TP31
TP30
TP29
TP28
TP27
TP26
CRSTb {3,4,5,6,10,11,13}
I2S_SD_mic7 {3,8}
4

Figure A.2. iCE40UP5K FPGA A - Display

© 2017-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
Note:
Place close
To Interconnects Page
to DUT
SPIVCCIO1_iCE_A
{3,4,5,6,11} CDONE
C9 C10 C11
10n 0.1u 1u
iCE_SS_A
{6} iCE_SS_A
iCE_SCK_A
{6} iCE_SCK_A
iCE_SI_A
{6} iCE_SI_A
iCE_SO_A
{6} iCE_SO_A
CRSTb_A
DSI_HS_CLKP
DSI_HS_D0P
DSI_HS_D0N
CDONE_A
proc_intr_A
Note:
DSI_HS_CLKN
Place close
to DUT
VCCIO2_iCE_A
C12 C13 C14
10n 0.1u 1u
DSI_LP_CLKP
DSI_LP_CLKN
DSI_LP_D0P
DSI_LP_D0N
SPIVCCIO1_iCE_A
R2
2k2
CDONE_A
D1
GREEN
DONE_A
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Place MIPI TX resistor network as close to bank 1 as possible.
Trace match *HS* P & N channels as well as individual pairs.
Minimize routing and trace match *LP* signals..
VCC3V3
J31
UART_RX_A 1 2
UART_TX_A iCE_SS_A
3 4
OSC_CLK_A 5 6 iCE_SCK_A
proc_cs_A iCE_SI_A
7 8
SPARE_A0 9 10 iCE_SO_A
SPARE_A1 CRSTb_A
11 12
SPARE_A2
13 14
15 16
17 18
19 20 proc_intr_A
21 22
23 24
CON24A
3
iCE40 UltraPlus Mobile Development Platform
Evaluation Board User Guide
2 1
Function Mapping from iCE40UP to Board
CDONE
iCE_SS_A
iCE_SCK_A
iCE_SI_A
iCE_SO_A
UART_TX_A
R19 0
UART_RX_A
R141 0
proc_cs_A
R142 0 DNI
proc_intr_A R143 0 DNI
OSC_CLK_A
R15 0
To Display Connect Page
DSI_LP_D0P DSI_D0P
R36 R0201
30 5%
DSI_HS_D0P
R39 R0201
1K 5%
DSI_HS_D0N DSI_D0N
R34 R0201
1K 5%
DSI_LP_D0N
R33 R0201
30 5%
DSI_LP_CLKP DSI_CLKP
R46 R0201
30 5%
DSI_HS_CLKP
R71 R0201
1K 5%
DSI_HS_CLKN DSI_CLKN
R38 R0201
1K 5%
DSI_LP_CLKN
R72 R0201
30 5%
0201
Place close to ICE40
SPARE_A0
SPARE_A1
SPARE_A2
LATTICE SEMICONDUCTOR CORPORATION CONFIDENTIAL
iCE40 UltraPlus Mobile Development Platform
Title Title Title
iCE40UP5K FPGA A - Display iCE40UP5K FPGA A - Display iCE40UP5K FPGA A - Display
Size Size Size Document Number Document Number Document Number
B B B
Date: Date: Date: Friday, November 03, 2017 Friday, November 03, 2017 Friday, November 03, 2017 Sheet Sheet Sheet
2 1
D
UART_TX {3,4,5,6,10,13}
UART_RX {3,4,5,6,10,13}
proc_cs {3,4,5,6,10}
proc_intr {3,4,5,6,10}
OSC_CLK {3,4,5,8,10,13}
DSI_D0P {7}
C
DSI_D0N {7}
DSI_CLKP {7}
DSI_CLKN {7}
B
SPARE_A0 {7,13}
SPARE_A1 {7,13}
SPARE_A2 {7,13}
A
Rev Rev Rev
D D D
2 2 2 of of of 14 14 14
23