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5
VCCIO0
MAKE PWR TRACES
CAPABLE OF 1A
J2
2
1
PT17C_INITn
4
3
PT17A
6
5
8
7
PT16C
10
9
PT16A
12
11
PT15C_JTAGen
14
13
16
15
PT15A
18
17
20
19
PT12C_SCL_PCLT0_0
22
21
PT12A_PCLKT0_1
24
23
26
25
PT11C_TCK_TESTCLK
28
27
PT11A
30
29
PT10C_TDO
32
31
34
33
PT10A
36
35
PT9C
PT9A
38
37
40
39
Header2x20
DNI
Note:
1. The Pin Functions indicated in the schematic symbol U3 are for LCMXO2-1200ZE-1TG144C. For the Pin Functions of the board with
LCMXO2-7000HE-4TG144C, refer to the pinout file.
5
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3
4
+3.3V
R22
R23
2k2
2k2
PT17D_DONE
PT17C_INITn
PT17B
PT17D_DONE
PT17A
PT17B
PT16D
PT16D
PT16C
PT16B
PT16B
PT15D_PROGn
PT16A
PT15B
PT15D_PROGn
PT12D_SDA_PCLKC0_0
PT15C_JTAGen
PT12B_PCLKC0_1
PT15B
PT15A
PT11D_TMS
PT11B
PT12D_SDA_PCLKC0_0
PT10D_TDI
PT12C_SCL_PCLT0_0
PT12B_PCLKC0_1
PT10B
PT12A_PCLKT0_1
PT9D
PT9B
PT11D_TMS
2
TMS
PT11C_TCK_TESTCLK
2
TCK
PT11B
PT11A
PT10D_TDI
2
TDI
PT10C_TDO
2
TDO
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
VCCIO0
C17
C18
C19
C20
0.01uF
0.1uF
0.1uF
0.1uF
+3.3V
VCCIO0
R24
1
4
3
U3-2
1
BANK 0
BANK 1
109
73
PR10D
PT17D/DONE
PR10D
110
74
PR10C
PT17C/INITn
PR10C
111
75
PR10B
PT17B
PR10B
112
76
PR10A
PT17A
PR10A
113
77
PR9D
PT16D
PR9D
114
78
PR9C
PT16C
PR9C
115
81
PR9B
PT16B
PR9B
117
82
PR9A
PT16A
PR9A
119
83
PR8D
PT15D/PROGRAMn
PR8D
120
84
PR8C
PT15C/JTAGENB
PR8C
121
85
PR8B
PT15B
PR8B
122
86
PR8A
PT15A
PR8A
125
87
PT12D/SDA/PCLKC0_0
NC4
126
89
PT12C/SCL/PCLKT0_0
NC5
127
PT12B/PCLKC0_1
128
91
PCLKC1_PR5D
PT12A/PCLKT0_1
PCLKC1_0/PR5D
92
PCLKT1_PR5C
PCLKT1_0/PR5C
130
93
PR5B
PT11D/TMS
PR5B
131
94
PR5A
PT11C/TCK/TEST_CLK
PR5A
132
PT11B
133
95
PR4D
PT11A
PR4D
96
PR4C
PR4C
136
97
PR4B
PT10D/TDI
PR4B
137
98
PR4A
PT10C/TDO
PR4A
138
PT10B
139
99
PR3B
PT10A
PR3B
100
PR3A
PR3A
140
PT9D
141
103
PT9C
NC6
142
PT9B
143
104
PR2D
PT9A
PR2D
105
PR2C
PR2C
106
PR2B
PR2B
107
PR2A
PR2A
118
79
VCCIO0
VCCIO1
123
88
C21
VCCIO0
VCCIO1
135
102
VCCIO0
VCCIO1
0.01uF
LCMXO2-1200ZE-1TG144C
3
Figure A.3. FPGA
MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
2
1
VCCIO1
VCC_1.2V
MAKE PWR TRACES
CAPABLE OF 1A
J3
RS232_Rx_TTL
2
RS232_Tx_TTL
2
RTSn
2
2
1
CTSn
2
4
3
PR10D
6
5
DSRn
2
PR10B
8
7
DCDn
2
10
9
DTRn
2
PR9D
12
11
PR9B
14
13
16
15
18
17
PR8D
20
19
PR8B
22
21
24
23
PCLKC1_PR5D
PCLKT1_PR5C
26
25
PR5B
28
27
30
29
PR4D
32
31
PR4B
34
33
PR3B
36
35
PR2D
38
37
PR2B
40
39
LED0
5
Header2x20
LED1
5
DNI
LED2
5
LED3
5
LED4
5
LED5
5
LED6
5
LED7
5
VCCIO1
C22
C23
C24
0.1uF
0.1uF
0.1uF
+3.3V
VCCIO1
R25
1
AXELSY
AXELSY
AXELSYS
S S
i i T T T it t t l l l e e e
Lattice MachXO2 1200ZE Breakout Board - FPGA
i i S S S iz z z e e e
Document Number
B B B
L L L CMX X
C C
M M XO O O 2 2 2 - - - 1 1 1 200ZE E
200Z
200ZE- - - B B B - - - E E E V V V N N N
D D D at t t e e e : : :
a a
S S S h h h e e e e e e t t t
Thursday, April 21, 2011
2
1
C15
0.1uF
PR10C
PR10A
PR9C
PR9A
PR8C
PR8A
PR5A
PR4C
PR4A
PR3A
PR2C
PR2A
3 3 3
f f o o o f
5 5 5
27
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