Lattice Semiconductor MachXO2 Breakout Board User Manual page 4

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
Figures
Figure 2.1. MachXO2 Breakout Board, Top Side ................................................................................................................... 7
Figure 6.1. Demonstration Design Block Diagram ................................................................................................................ 9
Figure 7.1. MachXO2 Breakout Board Block Diagram ........................................................................................................ 12
Figure 7.2. J3/J4 Header Landing Callout ............................................................................................................................ 18
Figure 7.3. J3/J5 Header Landing Callout ............................................................................................................................ 18
Figure 7.4. J1 Header Landing and LED Array Callout ......................................................................................................... 19
Figure A.1. Block Diagram ................................................................................................................................................... 25
Figure A.2. USB Interface to JTAG ....................................................................................................................................... 26
Figure A.3. FPGA ................................................................................................................................................................. 27
Figure A.4. FPGA ................................................................................................................................................................. 28
Figure A.5. Power LEDs ....................................................................................................................................................... 29
Tables
Table 7.1. Breakout Board Components and Interfaces ..................................................................................................... 13
Table 7.2. Expansion Connector Reference ........................................................................................................................ 13
Table 7.3. Expansion Header Pin Information (J2) .............................................................................................................. 14
Table 7.3. Expansion Header Pin Information (J3) .............................................................................................................. 15
Table 7.4. Expansion Header Pin Information (J4) .............................................................................................................. 16
Table 7.7. MachXO2 and MachXO3 FPGA Interface Reference .......................................................................................... 19
Table 7.8. JTAG Interface Reference ................................................................................................................................... 19
Table 7.9. JTAG Programming Pin Informationz ................................................................................................................. 20
Table 7.10. LEDs .................................................................................................................................................................. 20
Table 7.12. Power and User LEDs Reference ...................................................................................................................... 20
Table 7.13. USB Interface Reference .................................................................................................................................. 20
Table 9.1. Ordering Information ......................................................................................................................................... 23
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4 FPGA-EB-02051-2.3