Programming/Fpga Configuration - Lattice Semiconductor LatticeECP3 User Manual

Table 3. Power Supply Test Connections
PCI Express Power Interface
Power can be sourced to the board via the PCB edge fingers (CN1). This interface allows the user to provide power
from a PCI Express host board.
Power Management
The evaluation board includes a Lattice ispPAC
This device controls the power sequence and monitors designated board supplies. The POWER GOOD indication
LEDS are controlled via this device.
The power management device is factory programmed to control the power supplies. A block diagram of the power
management is shown in Figure 3.
Figure 3. Power Management Block Diagram

Programming/FPGA Configuration

(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
Note: An ispDOWNLOAD™ Cable is included with each ispLEVER
shipment. Cables may also be purchased separately from Lattice.
ispVM Download Interface
J12 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.
Test Point Designator
LP1
LP2
LP3
LP4
LP5
LP6
VCC Core, +1.2v , 10A
12V INPUT
POL
PCIe Edge
12V Wall Adapter
12V Input Terminal
3.3VIN, +2.5V, 6A
POL
ispPAC
LatticeECP3 Serial Protocol Board – Revision E
Supply
2.5V
1.5V
3.3V
1.8V
1.2V VCCA
1.2V VCC Core
®
-POWR1220AT8 programmable power management IC (U10).
LDO 1_5V, +1.5V, 2A
LDO 1_8V, +1.8V, 2A
LDO 1_2VA, +1.2V, 1.5A
LDO
LDO
2_5V, +2.5V, 1.5A
MOSFET
3_3V, +3.3V, 2A
®
-Base or ispLEVER-Advanced design tool
5
ETH_1_2V, +1.2V, 0.5A
User's Guide