Part 3.21: Dip Switch Configuration - Alinx ZYNQ UltraScale+ User Manual

ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
Figure 3-20-1: Rest keys connection diagram
ZYNQ pin assignment of keys
Signal Name ZYNQ Pin Name ZYNQ Pin Number Description
PS_KEY1 PS_MIO26 L15 PS KEY1 Input
PL_KEY1 B44_L1_N AE14 PL KEY1 Input

Part 3.21: DIP Switch Configuration

There is a 4-digit DIP switch SW1 on the FPGA development board to
configure the startup mode of the ZYNQ system. The AXU5EV-P system
development platform supports 4 startup modes. The 4 startup modes are
JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After
ZU4EV chip is powered on, it will detect the level of (PS_MODE0~3) to
determine the startup mode. The user can select different startup modes
through the DIP switch SW1 on the expansion board. The SW1 startup mode
configuration is shown in the following table 3-21-1.
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