Part 2.3: Ddr4 Dram - Alinx ZYNQ UltraScale+ User Manual

Sata 3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
 Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
 Power management: Support the four-part division of power supply
Full/ Low/ PL/ Battery
 Encryption algorithm: support RSA, AES and SHA.
 System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
 System Logic Cells: 256.2K
 CLB Flip-flops: 234.24K
 Look-up-tables (LUTs): 117.12K
 Block RAM: 5.1 Mb
 Clock Management Units (CMTs): 4
 DSP Slices: 1248
 Video Codec Unit (VCU): 1
 PCIE3.0: 2
 GTH 12.5Gb/s Transceiver: 4
XCZU5EV-2SFVC784I chip speed grade is -2, industrial grade, package is
SFVC784

Part 2.3: DDR4 DRAM

The ACU5EV core board is equipped with 5 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. One DDR4
chip is mounted on the PL end, which is a 16-bit data bus width and a capacity
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
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