Part 3.13: 485 Communication Interface - Alinx ZYNQ UltraScale+ User Manual

PS_CAN2_TX
PS_CAN2_RX

Part 3.13: 485 Communication Interface

There are two 485 communication interfaces on the AXU5EV-P carrier
board. The 485 communication port 1 is connected to the IO interface of
BANK43~45 on the PL system. The 485 transceiver chip selects the MAX3485
chip from MAXIM for the user's 485 communication service.
Figure 3-13-1 is the connection diagram of the 485 transceiver chip on the
PL side
Figure 3-13-1: 485 Communication on the PL Side
The 485 communication pins are assigned as follows:
Signal Name
PL_485_TXD1
PL_485_RXD1
PL_485_DE1
PL_485_TXD2
PL_485_RXD2
PL_485_DE2
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
PS_MIO39
PS_MIO38
Pin Name Pin Number
B43_L1_P
B43_L1_N
B45_L10_N
B43_L3_N
B43_L3_P
B45_L10_P
H19
H18
AG10 The 1
AH10 The 1
A10 The 1 st Channel 485 Transmit Enable
AH11 The 2 nd
AH12 The 2
B11 The 2 Channel 485 Transmit Enable
nd
CAN2 Transmitter
CAN2 Receiver
Description
Channel 485 Transceiver
st
Channel 485 Receiver
st
Channel 485 Transceiver
Channel 485 Receiver
nd
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