Part 3.12: Can Communication Interface - Alinx ZYNQ UltraScale+ User Manual

PCIE_RX1_N
PCIE_RX1_P
PCIE_TX0_N
PCIE_TX0_P
PCIE_TX1_N
PCIE_TX1_P
PCIE_PERST

Part 3.12: CAN Communication Interface

There are 2 CAN communication interfaces on the AXU5EV-P carrier
board, which are connected to the MIO interface of the BANK501 on the PS
system side. The CAN transceiver chip selected TI's SN65HVD232C chip for
user CAN communication services. The connection of the CAN transceiver
chip on the PS side is show as Figure 3-12-1
Figure 3-12-1: Connection diagram of CAN transceiver chip on PS side
The CAN communication pin assignments are as follows:
Signal Name
PS_CAN1_TX
PS_CAN1_RX
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
224_RX3_N
224_RX3_P
224_TX2_N
224_TX2_P
224_TX3_N
224_TX3_P
B43_L8_N
ZYNQ Pin Name
PS_MIO32
PS_MIO33
P1 PCIE Channel 1 Data Receive Negative
P2 PCIE Channel 1 Data Receive Positive
R3 PCIE Channel 0 Data Transmit Negative
R4 PCIE Channel 0 Data Transmit Positive
N3 PCIE Channel 1 Data Transmit Negative
N4 PCIE Channel 1 Data Transmit Positive
AC11 PCIE Board Reset Signal
ZYNQ Pin Number
J16
L16
Description
CAN1 Transmitter
CAN1 Receiver
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