Alinx AXU2CGA User Manual
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Alinx AXU2CGA User Manual

Zynq ultrascale+ fpga development board
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ZYNQ UltraScale+
FPGA Development Board
AXU2CGA/B
User Manual

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Summary of Contents for Alinx AXU2CGA

  • Page 1 ZYNQ UltraScale+ FPGA Development Board AXU2CGA/B User Manual...

  • Page 2: Version Record

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Version Record Version Date Release By Description Rev 1.0 2021-04-08 Rachel Zhou First Release Amazon Store: https://www.amazon.com/alinx 2 / 29...

  • Page 3: Table Of Contents

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Table of Contents Version Record.......................2 Part 1: AXU2CGA/B Introduction................ 4 Part 2: ZYNQ Chip....................5 Part 3: DDR4 DRAM..................... 7 Part 4: QSPI Flash....................11 Part 5: eMMC Flash (Only for AXU2CGB)............12 Part 6: EEPROM....................13 Part 7: DP Display Interface................

  • Page 4: Part 1: Axu2Cga/B Introduction

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 1: AXU2CGA/B Introduction The AXU2CGA/B Board is characterized by its small size and extensive peripherals. The main chip is Xilinx's Zynq UltraScale+ MPSoCs CG family chip, the model is XCZU2CG-1SFVC784E. The PS side of AXU2CGA is mounted with 2 slices of DDR4 (total 1GB, 32bit) and 1 slice of 256Mb QSPI FLASH.

  • Page 5: Part 2: Zynq Chip

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 2: ZYNQ Chip The PS system of the XCZU2CG-1SFVC784E chip integrates two ARM Cortex™-A53 processors with a speed of up to 1.2Ghz and supports Level 2 Cache; it also contains two Cortex-R5 processors with a speed of up to 500Mhz.
  • Page 6 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual The main parameters of the PS system are as follows:  ARM dual-core Cortex ™ -A53 processor, speed up to 1.2GHz, each CPU 32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2 CPUs ...

  • Page 7: Part 3: Ddr4 Dram

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 3: DDR4 DRAM There are two Micron DDR4 chips on the PS side of the AXU2CGA board, which form a 32-bit data bus bandwidth and a total capacity of 1GB. There are 4 Micron DDR4 chips on the PS side of the AXU2CGB board, which form a 64-bit data bus bandwidth and a total capacity of 2GB.
  • Page 8 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26 PS_DDR4_DQS3_P PS_DDR_DQS_P3_504 AE27 PS_DDR4_DQS3_N PS_DDR_DQS_N3_504 AF27 PS_DDR4_DQ0 PS_DDR_DQ0_504 AD21 PS_DDR4_DQ1 PS_DDR_DQ1_504 AE20 PS_DDR4_DQ2 PS_DDR_DQ2_504 AD20 PS_DDR4_DQ3 PS_DDR_DQ3_504 AF20 PS_DDR4_DQ4 PS_DDR_DQ4_504 AH21 PS_DDR4_DQ5 PS_DDR_DQ5_504 AH20 PS_DDR4_DQ6 PS_DDR_DQ6_504...
  • Page 9 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual PS_DDR4_DM0 PS_DDR_DM0_504 AG20 PS_DDR4_DM1 PS_DDR_DM1_504 AE23 PS_DDR4_DM2 PS_DDR_DM2_504 AE25 PS_DDR4_DM3 PS_DDR_DM3_504 AE28 PS_DDR4_A0 PS_DDR_A0_504 PS_DDR4_A1 PS_DDR_A1_504 PS_DDR4_A2 PS_DDR_A2_504 AB28 PS_DDR4_A3 PS_DDR_A3_504 AA28 PS_DDR4_A4 PS_DDR_A4_504 PS_DDR4_A5 PS_DDR_A5_504 AA27 PS_DDR4_A6 PS_DDR_A6_504 PS_DDR4_A7 PS_DDR_A7_504 AA23...
  • Page 10 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual AXU2CGB PS side DDR4 SDRAM data pin assignment is the same as AXU2CGA, additional data signal assignment is as follows: Signal Name Pin Name Pin Number PS_DDR4_DQS4_P PS_DDR_DQS_P4_504 PS_DDR4_DQS4_N PS_DDR_DQS_N4_504 PS_DDR4_DQS5_P PS_DDR_DQS_P5_504...

  • Page 11: Part 4: Qspi Flash

    PS_DDR_DM7_504 Part 4: QSPI Flash The AXU2CGA/B board has a 256MBit Quad-SPI FLASH chip, the model is MT25QU256ABA1EW9-0SIT. QSPI FLASH is connected to the GPIO port of BANK500 in the PS part of the ZYNQ chip. Figure 4-1 shows the part of QSPI Flash in the schematic.

  • Page 12: Part 5: Emmc Flash (Only For Axu2Cgb)

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual MIO2_QSPI0_IO2 PS_MIO2_500 AF15 MIO3_QSPI0_IO3 PS_MIO3_500 AH15 MIO4_QSPI0_IO0 PS_MIO4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 Part 5: eMMC Flash (Only for AXU2CGB) There is an eMMC FLASH chip with a capacity of 8GB on the AXU2CGB board.

  • Page 13: Part 6: Eeprom

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 6: EEPROM The AXU2CGA/B development board has a piece of EEPROM onboard, the model number is 24LC04. The I2C signal of the EEPROM is connected to the MIO port of the ZYNQ PS side. Figure 6-1 is EEPROM schematic:...
  • Page 14 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Figure 7-1: DP interface design Schematic The DisplayPort interface ZYNQ pin assignment is as follows: Signal Name ZYNQ Pin Number ZYNQ Description Number Low bits of DP Data GT0_DP_TX_P PS_MGTTXP3_505 Transmit Positive...

  • Page 15: Part 8: Usb 3.0 Interface

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 8: USB 3.0 Interface There are 4 USB3.0 interfaces on the AXU2CGA/B board, the interface is HOST working mode (Type A), and the data transmission speed is up to 5.0Gb/s. The USB3.0 interfaces connect external USB PHY chip and USB3.0 HUB chip through ULPI interface to realize high-speed USB3.0 data...

  • Page 16: Part 9: Gigabit Ethernet Interface

    USB2.0 the NEXT Data Signal Part 9: Gigabit Ethernet Interface There is 1 Gigabit Ethernet interface on AXU2CGA/B, and the Ethernet interface is on BANK502 of PS connected through GPHY chip. The GPHY chip uses the KSZ9031RNXIC Ethernet PHY chip from Micrel, and the PHY Address is 001.

  • Page 17: Part 10: Usb To Serial Port

    MDIO Management Data Part 10: USB to Serial Port There is a Uart to USB interface on the AXU2CGA/B board for system debugging. The conversion chip uses the USB-UAR chip of Silicon Labs CP2102, and the USB interface uses the MINI USB interface. It can be connected to the USB port of the PC with a USB cable for independent power supply of the core board and serial data communication.

  • Page 18: Part 11: Sd Card Slot Interface

    PL Uart Data Input Part 11: SD Card Slot Interface The AXU2CGA/B board contains a Micro SD card interface. The SDIO signal is connected to the IO signal of BANK501. The SD card connector schematic is shown in Figure 11-1.

  • Page 19: Part 12: Pcie Interface

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 12: PCIE Interface There is a PCIE x1 slot on the AXU2CGA/B board for connecting PCIE peripherals, and the PCIE communication speed is up to 5Gbps. PCIE signal is directly connected to LANE0 of BANK505 PS MGT transceiver. The schematic...

  • Page 20: Part 13: 40-Pin Expansion Header

    Part 13: 40-Pin Expansion Header The AXU2CGA/B board is reserved with two 0.1-inch standard pitch 40-pin expansion ports J12 and J15, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 21 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual IO1_3N IO1_3P IO1_4N IO1_4P IO1_5N IO1_5P IO1_6N IO1_6P IO1_7N IO1_7P IO1_8N IO1_8P IO1_9N IO1_9P IO1_10N IO1_10P IO1_11N IO1_11P IO1_12N IO1_12P IO1_13N IO1_13P IO1_14N IO1_14P IO1_15N IO1_15P IO1_16N IO1_16P IO1_17N IO1_17P VCC_3V3_BUCK4 VCC_3V3_BUCK4...

  • Page 22: Part 14: Mipi Camera Interface

    VCC_3V3_BUCK4 Part 14: MIPI Camera Interface There are 2 MIPI interfaces on the AXU2CGA/B board for connecting MIPI cameras. The differential signal of MIPI is connected to the HP IO of BANK64 and 65, and the level standard is +1.2V; the control signal of MIPI is connected to BANK24, and the level standard is +3.3V.
  • Page 23 ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Ground MIPI1_LAN1_N IO_L3N_64 MIPI Data 1 Signal N MIPI1_LAN1_P IO_L3P_64 MIPI Data 1 Signal P Ground MIPI1_CLK_N IO_L1N_64 MIPI Clock Signal N MIPI1_CLK_P IO_L1P_64 MIPI Clock Signal P Ground CAM1_GPIO IO_L2N_24 AH14...

  • Page 24: Part 15: Jtag Debug Port

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 15: JTAG Debug Port The 10-pin JTAG interface is reserved on the AXU2CGA/B board for downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. The pin definition of JTAG is shown in the figure below Figure 15-1: JTAG Pin Definition Amazon Store: https://www.amazon.com/alinx...

  • Page 25: Part 16: Dip Switch Configuration

    There are 4 user indicator lights, 4 user control KEYs and a reset KET on the AXU2CGA/B board. 4 user indicators and 4 user KEYs are all connected to the IO of BANK24. The schematic diagram of the LED light hardware connection is shown in Figure 17-1: Amazon Store: https://www.amazon.com/alinx...

  • Page 26: Part 18: System Clock

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Figure 17-1: LED Schematic LED and Key Pin Assignment: Signal Name Pin Name Pin Number LED1 IO_L9N_24 LED2 IO_L12P_24 LED3 IO_L12N_24 AA12 LED4 IO_L7N_24 AB13 KEY1 IO_L7P_24 AA13 KEY2 IO_L1N_24 AE14 KEY3...

  • Page 27: Part 19: Alinx Customized Fan Interface

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Figure 18-1: Clock Source Clock Pin Assignment: Signal Name Pin Name Pin Number PL_REF_CLK IO_L8P_44 AB11 The level of PL_REF_CLK is +1.8V. Part 19: ALINX Customized Fan Interface The fan is powered by 12V, and the speed can be adjusted through the FAN_PWM signal.

  • Page 28: Part 20: Power Input

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 20: Power Input The power input of AXU2CGA/B is an adapter with DC12V and current 2A. The power interface is shown in the figure below Figure 20-1: Power Input Interface Amazon Store: https://www.amazon.com/alinx...

  • Page 29: Part 21: Board Size Dimension

    ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual Part 21: Board Size Dimension Figure 21-1: Size Dimension (Top View) Amazon Store: https://www.amazon.com/alinx 29 / 29...

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