Part 3.16: Jtag Debug Port - Alinx ZYNQ UltraScale+ User Manual

FMC_LA30_N
FMC_LA31_P
FMC_LA31_N
FMC_LA32_P
FMC_LA32_N
FMC_LA33_P
FMC_LA33_N
FMC_PRSNT
PWRGD

Part 3.16: JTAG Debug Port

The JTAG interface is reserved on the AXU5EV- P expansion board for
downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In
order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ UltraScale+ chip.
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
B66_L13_N
B66_L9_P
B66_L9_N
B65_L24_P
B65_L24_N
B66_L8_P
B66_L8_N
B45_L12_N
B44_L2_N
Figure 3-16-1: JTAG Interface Schematic
D6 FMC Reference 30
B3 FMC Reference 31
A3 FMC Reference 31
H9 FMC Reference 32
H8 FMC Reference 32
A2 FMC Reference 33
A1 FMC Reference 33
C12 FMC Module Exist Signal
AH14 FMC Power Good Signal
Data N
th
Data P
st
st Data N
nd Data P
nd Data N
Data P
rd
Data N
rd
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