Table of Contents
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PS_DDR4_DQS7_P
PS_DDR4_DQS7_N
PS_DDR4_DQ0
PS_DDR4_DQ1
PS_DDR4_DQ2
PS_DDR4_DQ3
PS_DDR4_DQ4
PS_DDR4_DQ5
PS_DDR4_DQ6
PS_DDR4_DQ7
PS_DDR4_DQ8
PS_DDR4_DQ9
PS_DDR4_DQ10
PS_DDR4_DQ11
PS_DDR4_DQ12
PS_DDR4_DQ13
PS_DDR4_DQ14
PS_DDR4_DQ15
PS_DDR4_DQ16
PS_DDR4_DQ17
PS_DDR4_DQ18
PS_DDR4_DQ19
PS_DDR4_DQ20
PS_DDR4_DQ21
PS_DDR4_DQ22
PS_DDR4_DQ23
PS_DDR4_DQ24
PS_DDR4_DQ25
PS_DDR4_DQ26
PS_DDR4_DQ27
PS_DDR4_DQ28
PS_DDR4_DQ29
PS_DDR4_DQ30
PS_DDR4_DQ31
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
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PS_DDR_DQS_N7_504
PS_DDR_DQ0_504
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PS_DDR_DQ2_504
PS_DDR_DQ3_504
PS_DDR_DQ4_504
PS_DDR_DQ5_504
PS_DDR_DQ6_504
PS_DDR_DQ7_504
PS_DDR_DQ8_504
PS_DDR_DQ9_504
PS_DDR_DQ10_504
PS_DDR_DQ11_504
PS_DDR_DQ12_504
PS_DDR_DQ13_504
PS_DDR_DQ14_504
PS_DDR_DQ15_504
PS_DDR_DQ16_504
PS_DDR_DQ17_504
PS_DDR_DQ18_504
PS_DDR_DQ19_504
PS_DDR_DQ20_504
PS_DDR_DQ21_504
PS_DDR_DQ22_504
PS_DDR_DQ23_504
PS_DDR_DQ24_504
PS_DDR_DQ25_504
PS_DDR_DQ26_504
PS_DDR_DQ27_504
PS_DDR_DQ28_504
PS_DDR_DQ29_504
PS_DDR_DQ30_504
PS_DDR_DQ31_504
J26
J27
AD21
AE20
AD20
AF20
AH21
AH20
AH19
AG19
AF22
AH22
AE22
AD22
AH23
AH24
AE24
AG24
AC26
AD26
AD25
AD24
AG26
AH25
AH26
AG25
AH27
AH28
AF28
AG28
AC27
AD27
AD28
AC28
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