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PS_DDR4_CKE0
PL Side DDR4 SDRAM pin assignment:
Signal Name
PL_DDR4_DQS0_P
PL_DDR4_DQS0_N
PL_DDR4_DQS1_P
PL_DDR4_DQS1_N
PL_DDR4_DQ0
PL_DDR4_DQ1
PL_DDR4_DQ2
PL_DDR4_DQ3
PL_DDR4_DQ4
PL_DDR4_DQ5
PL_DDR4_DQ6
PL_DDR4_DQ7
PL_DDR4_DQ8
PL_DDR4_DQ9
PL_DDR4_DQ10
PL_DDR4_DQ11
PL_DDR4_DQ12
PL_DDR4_DQ13
PL_DDR4_DQ14
PL_DDR4_DQ15
PL_DDR4_DM0
PL_DDR4_DM1
PL_DDR4_A0
PL_DDR4_A1
PL_DDR4_A2
PL_DDR4_A3
PL_DDR4_A4
PL_DDR4_A5
PL_DDR4_A6
PL_DDR4_A7
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ZYNQ Ultrascale + FPGA Board AXU5EV-P User Manual
PS_DDR_CKE0_504
Pin Name
IO_L22P_T3U_N6_DBC_AD0P_64
IO_L22N_T3U_N7_DBC_AD0N_64
IO_L16P_T2U_N6_QBC_AD3P_64
IO_L16N_T2U_N7_QBC_AD3N_64
IO_L24N_T3U_N11_64
IO_L24P_T3U_N10_64
IO_L23N_T3U_N9_64
IO_L23P_T3U_N8_64
IO_L21N_T3L_N5_AD8N_64
IO_L21P_T3L_N4_AD8P_64
IO_L20N_T3L_N3_AD1N_64
IO_L20P_T3L_N2_AD1P_64
IO_L18N_T2U_N11_AD2N_64
IO_L18P_T2U_N10_AD2P_64
IO_L17N_T2U_N9_AD10N_64
IO_L17P_T2U_N8_AD10P_64
IO_L15N_T2L_N5_AD11N_64
IO_L15P_T2L_N4_AD11P_64
IO_L14N_T2L_N3_GC_64
IO_L14P_T2L_N2_GC_64
IO_L19P_T3L_N0_DBC_AD9P_64
IO_L13P_T2L_N0_GC_QBC_64
IO_L8N_T1L_N3_AD5N_64
IO_L3P_T0L_N4_AD15P_64
IO_L8P_T1L_N2_AD5P_64
IO_L3N_T0L_N5_AD15N_64
IO_L11P_T1U_N8_GC_64
IO_L4P_T0U_N6_DBC_AD7P_64
IO_L9N_T1L_N5_AD12N_64
IO_L2P_T0L_N2_64
V28
Pin Number
AE2
AF2
AD2
AD1
AG1
AF1
AH1
AH2
AF3
AE3
AH3
AG3
AC1
AB1
AC2
AB2
AB3
AB4
AC3
AC4
AG4
AD5
AG8
AB8
AF8
AC8
AF7
AD7
AH7
AE9
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