Pcie Timing - Quectel RM510Q-GL Hardware Design

4.3.4. PCIe Timing

The following figure is PCIe power-up timing sequence for an adapter powered from system power rail in
PCI Express M.2 specification.
Figure 20: PCIe Power-up Timing Sequence of M.2 Specification
The following table is power-up timing variables in PCI Express M.2 specification.
Table 17: PCIe Power-up Timing Variables of M.2 Specification
Symbol Min.
50 ms
T
PVPGL
100 μs
T
PERST#-CLK
RFFE_VIO_1V8
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_REFCLK
Figure 21: PCIe Power-up Timing Sequence of the Module
RM510Q-GL_Hardware_Design
Typ.
-
-
Module power-on or insertion detection
VCC
RESET#
System turn-on and booting
FCPO#
T
FCPO#-CLKREQ#
T T
power-on turn-on
Max. Comment
- Power valid to PERST# Input inactive
- REFCLK stable before PERST# inactive
> 90 ms
T > 100 ms
FCPO#-PERST#
T
PERST#-CLK
5G Module Series
RM510Q-GL Hardware Design
3.7 V
1.5 V
≥ 1.19 V
V
IH
1.8 V
> 100 μs
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