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PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 19: Pin Definition of PCM Interface
Pin No. Pin Name
20
PCM_CLK
22
PCM_DIN
24
PCM_DOUT
28
PCM_SYNC
The clock and mode can be configured by AT command, and the default configuration is slave mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [5] for details about AT+QDAI command.
RM510Q-GL_Hardware_Design
1
2
MSB
MSB
Figure 22: Primary Mode Timing Sequence
1
2
MSB
MSB
Figure 23: Auxiliary Mode Timing Sequence
I/O
Description
DIO, PD
PCM data bit clock
DI, PD
PCM data input
DO, PD
PCM data output
DIO, PD
PCM data frame sync
RM510Q-GL Hardware Design
125 μs
255
LSB
LSB
125 μs
31
5G Module Series
256
MSB
MSB
32
LSB
MSB
LSB
MSB
DC Characteristics
1.8 V
1.8 V
1.8 V
1.8 V
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