Functional Diagram - Quectel RM510Q-GL Hardware Design

5g module series
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2.4. Functional Diagram

The following figure shows a block diagram of RM510Q-GL.
Power management
Baseband
LPDDR4X SDRAM + NAND Flash
Radio frequency
M.2 Key-B interface
VCC
GND
FULL_CARD_POWER_OFF#
RESET#
(U)SIM1
USB 2.0 & USB 3.1
PCIe 3.0
×
1
RFFE
GPIOs
WWAN_LED#
WAKE_ON_WAN#
W_DISABLE1#
W_DISABLE2#
RM510Q-GL_Hardware_Design
PMIC
38.4MHz XO
MCP
NAND 4Gb x 8
Clock IC
LPDDR4X 4Gb x 16
Control
Baseband
Control
Figure 1: Functional Diagram
RM510Q-GL Hardware Design
Tx
PRx
Qlink
DRx
Qlink
mmWave
Transceiver
5G Module Series
ANT3_GNSSL1
ANT2
ANT1
ANT0
IFV4
IFH1
IFH2
IFV3
IFV2
IFH3
IFV1
IFH4
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