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28
PCM_SYNC
29
USB_SS_TX_M
30
USIM1_RST
31
USB_SS_TX_P
32
USIM1_CLK
33
GND
34
USIM1_DATA
35
USB_SS_RX_M
36
USIM1_VDD
37
USB_SS_RX_P
38
SDX2AP_STATUS*
39
GND
40
QTM0_PON
41
PCIE_TX_M
42
QTM1_PON
43
PCIE_TX_P
44
QTM2_PON
45
GND
46
QTM3_PON
47
PCIE_RX_M
48
QTM_VDD_1V9
49
PCIE_RX_P
50
PCIE_RST_N
RM510Q-GL_Hardware_Design
DIO,
PCM data frame sync
PD
USB 3.1 super-speed
AO
transmit (-)
DO,
(U)SIM1 card reset
PD
USB 3.1 super-speed
AO
transmit (+)
DO,
(U)SIM1 card clock
PD
Ground
DIO,
(U)SIM1 card data
PU
USB 3.1 super-speed
AI
receive (-)
Power supply for (U)SIM1
PO
card
USB 3.1 super-speed
AI
receive (+)
DO,
Status indication to AP
PD
Ground
DO
mmWave antenna control 0 1.8 V
AO
PCIe transmit (-)
DO
mmWave antenna control 1 1.8 V
AO
PCIe transmit (+)
DO
mmWave antenna control 2 1.8 V
Ground
DO
mmWave antenna control 3 1.8 V
AI
PCIe receive (-)
Power supply for mmWave
PO
antenna modules
AI
PCIe receive (+)
DI,
PCIe reset.
OD
Active LOW
5G Module Series
RM510Q-GL Hardware Design
1.8 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
USIM1_VDD
1.8/3.0 V
1.8 V
22 / 87
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