Quectel RM510Q-GL Hardware Design page 36

5g module series
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The timing sequence of reset scenario is illustrated by the following figure.
VCC(H)
RESET#
FCPO#(H)
RFFE_VIO_1V8
USIM_VDD
Module Status
Table 13: Resetting Timing of the Module
Symbol
Min.
T
200 ms
RST#-USIM
T
250 ms
RST#
RM510Q-GL_Hardware_Design
3.7 V
1.5 V
≥ 1.19 V
V
IH
T
RST#-USIM
1.8 V
1.8 V or 3.0 V
Running
Figure 14: Reset Timing Sequence of the Module
Typ.
Max.
-
-
400 ms
600 ms
RM510Q-GL Hardware Design
Resetting
250 ms ≤ T
≤ 600 ms
RST#
Comment
(U)SIM card turn-off time
T
600 ms will lead to repeated module reset.
RST#
5G Module Series
Restarting
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