Quectel RM510Q-GL Hardware Design page 32

5g module series
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It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF#. A simple reference circuit
is illustrated by the following figure.
Host
GPIO
NOTE:
The voltage of pin 6 should be no less than 1.19 V when it is at high level.
The timing sequence of turn-on scenario is illustrated by the following figure.
VCC
RESET#
FCPO#
RFFE_VIO_1V8
USIM_VDD
Module Status
Table 9: Turn-on Timing of the Module
Symbol
Min.
T
0 ms
power-on
RM510Q-GL_Hardware_Design
1.8 V or 3.3 V
Figure 8: Turn on the Module with a Host GPIO
Module power-on or insertion detection
System turn-on and booting
68 ms
Inactive
T
T
power-on
turn-on
Figure 9: Turn-on Timing Sequence of the Module
Typ.
Max.
20 ms
-
FULL_CARD_POWER_OFF#
20 s
System booting
T
booting
Comment
Module power-on time depending on the host.
5G Module Series
RM510Q-GL Hardware Design
Module
6
R1
PMIC
100k
3.7 V
1.5 V
≥ 1.19 V
V
IH
1.8 V
1.8 V or 3.0 V
Active
T
registering
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