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To ensure the signal integrity of PCIe interface, AC coupling capacitors C5 and C6 should be placed close
to the host on PCB. C1 and C2 have been embedded into the module, so do not place these two
capacitors on your schematic and PCB.
The following principles of PCIe interface design should be complied with, so as to meet PCIe
specification.
⚫
Keep the PCIe data and control signals away from sensitive circuits and signals, such as RF, audio,
crystal and oscillator signals.
⚫
Add a capacitor in series on Tx/Rx traces to prevent any DC bias.
⚫
Keep the maximum trace length less than 300 mm.
⚫
Keep the length matching of each differential data pair (Tx/Rx) less than 0.7 mm for PCIe routing
traces.
⚫
Keep the differential impedance of PCIe data trace as 85 Ω ±10 %.
⚫
You must not route PCIe data traces under components or cross them with other traces.
4.3.4. PCIe Timing
Table 17: PCIe Power-up Timing of M.2 Specification
Symbol
Min.
50 ms
T
PVPGL
100 μs
T
PERST#-CLK
RM510Q-GL_Hardware_Design
Figure 20: PCIe Power-up Timing of M.2 Specification
Typ.
Max.
-
-
-
-
RM510Q-GL Hardware Design
Comment
Power Valid to PERST# Input inactive
REFCLK stable before PERST# inactive
5G Module Series
44 / 88
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