Pcie Timing - Quectel 5G Series Hardware Design

4.3.4. PCIe Timing

The following figure is PCIe power-up timing sequence for an adapter powered from system power rail in
PCI Express M.2 specification.
Figure 20: PCIe Power-on Timing Requirements of M.2 Specification
The following table is power-up timing variables in PCI Express M.2 specification.
Table 17: Power-up Timing of M.2 Specification
Symbol Min.
T 50 ms
PVPGL
100 μs
T
PERST#-CLK
RM500Q-GL_Hardware_Design
Typ. Max.
- -
- -
RM500Q-GL Hardware Design
Comment
Power valid to PERST# input inactive
REFCLK stable before PERST# inactive
5G Module Series
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