Lcd Interface Timing - 8-Bit Single Color Panels Format 1 - Epson S1D13503 Series Technical Manual

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LCD Interface Timing - 8-Bit Single Color Panels Format 1

YD
LP
LP
XSCL2
(WF)
XSCL
UD/LD
Figure 7-17 LCD Interface Timing - 8-Bit Single Color Panels Format 1
Table 7-16 LCD Interface Timing - 8-Bit Single Color Panels Format 1
Symbol
t
LP period
1
t
YD hold from LP falling edge
2
t
LP pulse width
3
t
LP setup to XSCL falling edge
6a
t
LP setup to XSCL2 falling edge
6b
t
XSCL falling edge to LP falling edge
7a
t
XSCL2 falling edge to LP falling edge
7b
t
LP falling edge to XSCL falling edge
8a
t
LP falling edge to XSCL2 falling edge
8b
t
XSCL period
9a
t
XSCL2 period
9b
t
XSCL high width
10a
t
XSCL2 high width
10b
t
XSCL low width
11a
t
XSCL2 low width
11b
t
UD/LD setup to XSCL falling edge
12a
t
UD/LD setup to XSCL2 falling edge
12b
t
UD/LD hold from XSCL falling edge
13a
t
UD/LD hold from XSCL2 falling edge
13b
t
LP falling edge to XSCL rising edge
14a
t
LP falling edge to XSCL2 rising edge
14b
Where t = 1/f
OSC
where HT = (number of horizontal panel pixels) ∗ t
where HNDP = horizontal non-display period in units of t
details).
** 5V operation, for 3.0V and 3.3V operation t
1-30
t
6a
t
6b
t
8b
t t
7b 14b
t t
7a 14a
t
Parameter
= input (pixel) clock period,
OSC
t
2
t
3
t
9b
t
11b
t
8a
t t t
12b 13b 12a 13a
1 2
,
OSC
(see Section 9.3 on page 57 for
OSC
will be 1.5t
12 OSC
t
1
t
10b
t
9a
t t
11a 10a
3
Min. Typ.
HT + HNDP - 10 –
t
13 - 10 –
OSC
t
5 - 5 –
OSC
t
22 - 5 –
OSC
t
19.5 - 5 –
OSC
t
20 - 5 –
OSC
t
23.5 - 5 –
OSC
t
17 - 5 –
OSC
t
14.5 - 5 –
OSC
t
4 - 5 –
OSC
t
4 - 5 –
OSC
t
- 5 –
OSC
t
- 5 –
OSC
t
3 - 10 –
OSC
t
3 - 10 –
OSC
t
1.5 - 10** –
OSC
t
1.5 - 10** –
OSC
t
- 5 –
OSC
t
- 5 –
OSC
t
16 - 10 –
OSC
t
13.5 - 10 –
OSC
- 24.
S18A-A-011-01
Max. Units
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns
– ns