Register Descriptions - Epson S1D13503 Series Technical Manual

EPSON
8 H
ARDWARE
The S1D13503 is configured and controlled via 16 internal 8-bit registers. There are two ways to
map these registers into the system I/O space.
1. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped
address (where base I/O address is selected by VD7–VD12, see Table 5-6.)
This scheme requires 16 sequential I/O addresses starting from the I/O mapped base address
selected by VD7–VD12 (see Table 5-6).
To perform an I/O access;
write data
read data
2. Indexing: I/O address = internal index register bits [3:0]
This scheme requires 2 sequential I/O addresses starting from the base address selected by VD4–
VD12 (see Table 5-6).
To perform an 8-bit I/O access;
write index IOW {I/O mapped address}, {index}
then
write data
or
read data
To perform a 16-bit I/O access;
write data
read data

8.1 Register Descriptions

AUX[00] Test Register
I/O address = 0000b, Read/Write
Test Mode Reserved
Enable
bit 7 Test Mode Enable
When this bit = 0 normal operation is enabled. When this bit = 1 the chip is placed in a
special test mode. The test input bits and test output bits (bits 6:0) are used to select vari-
ous internal test functions.
bit 6 Reserved
During normal operation this bit must = 0.
bits 5–0 Test Mode Input and Output Bits [2:0]
When bit 7 = 1 these are the Test Input Select Input and Output bits. When bits 6 and 7 =
0 (normal operation) these bits may be used as read/write scratch registers.
1-38
R
EGISTER
IOW {absolute I/O address}, {data}
IOR {absolute I/O address}
IOW {I/O mapped address +1}, {data}
IOR {I/O mapped address +1}
IOW {I/O mapped address}, {index,data} ; write the index and data of the
IOW {I/O mapped address}, {index}
IOR {I/O mapped address +1}
Test Input Test Input
Select Bit 2 Select Bit 1
I
NTERFACE
; write the index of the register to be
accessed
; write data to the indexed register
; read the indexed register
register to be accessed
; write to the indexed register
; read the indexed register
Test Input Test Output
Select Bit 0 Select Bit 2
Test Output Test Output
Select Bit 1 Select Bit 0
S18A-A-011-01