Epson S1D13503 Series Technical Manual page 146

EPSON
S1D13503 R
AUX[01] Mode Register 0: I/O address = 0001b, RW
DISP PANEL
AUX[02] Line Byte Count Register (LSB): I/O address = 0010b, RW
Bit 7 Bit 6
AUX[03] Mode Register 1: I/O address = 0011b, RW
Power Save Mode
Bit 1 Bit 0
AUX[04] Total Display Line Count Register (LSB): I/O address = 0100b, RW
Bit 7 Bit 6
AUX[05] Total Display Line Count Register (MSB) and WF Count Register: I/O address = 0101b, RW
Bit 5 Bit 4
AUX[06] Screen 1 Display Start Address Register (LSB): I/O address = 0110b, RW
Bit 7 Bit 6
AUX[07] Screen 1 Display Start Address Register (MSB): I/O address = 0111b, RW
Bit 15 Bit 14
AUX[08] Screen 2 Display Start Address Register (LSB): I/O address = 1000b, RW
Bit 7 Bit 6
AUX[09] Screen 2 Display Start Address Register (MSB): I/O address = 1001b, RW
Bit 15 Bit 14
AUX[0A] Screen 1 Display Line Count Register (LSB): I/O address = 1010b, RW
Bit 7 Bit 6
AUX[0B] Screen 1 Display Line Count Register (MSB): I/O address = 1011b, RW
1
n/a n/a
AUX[0C] Horizontal Non-Display Period Register: I/O address = 1100b, RW
Bit 7 Bit 6
AUX[0D] Address Pitch Adjustment Register: I/O address = 1101b, RW
Bit 7 Bit 6
AUX[0E] Look-Up Table Address Register: I/O address = 1110b, RW
Green Bank Select
Bit 1 Bit 0
AUX[0F] Look-Up Table Data Register: I/O address = 1111b, RW
Red Bank Select
Bit 1 Bit 0
Notes: 1. n/a bits should be written 0.
2. These bits are used to identify the S1D13503 at power on / RESET. If these bits read 00b at Power On / Re-
set the device is an S1D13503. If this bit reads 10b at Power On / Reset the device is an SED1352F
D . If this bit reads 11b at Power On / Reset the device is an SED1352F
0B
2-70
S
EGISTER
Mask XSCL LCDE
Line Byte Count (low byte)
Bit 5 Bit 4
LCD Signal
LUT Bypass
State
Total Display Line Count (low byte)
Bit 5 Bit 4
WF Count
Bit 3 Bit 2
Screen 1 Display Start Address (low byte)
Bit 5 Bit 4
Screen 1 Display Start Address (high byte)
Bit 13 Bit 12
Screen 2 Display Start Address (low byte)
Bit 5 Bit 4
Screen 2 Display Start Address (high byte)
Bit 13 Bit 12
Screen 1 Display Line Count (low byte)
Bit 5 Bit 4
n/a n/a
Horizontal Non-Display Period
Bit 5 Bit 4
Address Pitch Adjustment
Bit 5 Bit 4
2
ID / RGB Index
Bit 1 Bit 0
Blue Bank Select
Bit 1 Bit 0
UMMARY
Gray Shade / LCD Data
Color Width Bit 0
Bit 3 Bit 2
LCD Data BW / 256
Width Bit 1 Colors
Bit 3 Bit 2
Bit 1 Bit 0
Bit 3 Bit 2
Bit 11 Bit 10
Bit 3 Bit 2
Bit 11 Bit 10
Bit 3 Bit 2
n/a n/a
Bit 3 Bit 2
Bit 3 Bit 2
Look-Up Table (Palette) Address
Bit 3 Bit 2
Look-Up Table (Palette) Data
Bit 3 Bit 2
0A
Memory
RAMS
Interface
Bit 1 Bit 0
Line Byte
Color Mode
Count Bit 8
Bit 1 Bit 0
Total Display Line Count
Bit 9 Bit 8
Bit 1 Bit 0
Bit 9 Bit 8
Bit 1 Bit 0
Bit 9 Bit 8
Bit 1 Bit 0
Screen 1 Disp Line Count
Bit 9 Bit 8
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
/F /D .
1A 0A
S18A-G-002-02
/F /
0B 1B