Avaya Communication Server 1000 Installation And Commissioning Manual page 43

- the lower left daughterboard (ports 0 and 1) is physically mapped to spans 5 and 6
of the PRI Gateway (MGC IPE card slots 5 and 6 from a system software
perspective)
- the lower right daughterboard (ports 0 and 1) is physically mapped to spans 7 and
8 of the PRI Gateway (MGC IPE card slots 7 and 8 from a system software
perspective)
• DDCH (using only port 1) interfaces can be defined and associated with E1/T1 spans
based on the following mapping rules:
- the upper left daughterboard (port 1) is physically mapped to span 2 of the PRI
Gateway (MGC IPE card slot 2 from a system software perspective)
- the upper right daughterboard (port 1) is physically mapped to span 4 of the PRI
Gateway (MGC IPE card slot 4 from a system software perspective)
- the lower left daughterboard (port 1) is physically mapped to span 6 of the PRI
Gateway (MGC IPE card slot 6 from a system software perspective)
- the lower right daughterboard (port 1) is physically mapped to span 8 of the PRI
Gateway (MGC IPE card slot 8 from a system software perspective)
• Because the DCHI daughterboard serves only one DCH interface (to support the DPNSS/
DASS protocol) only port 1 in the daughterboard can be used as DCH interface. The
following mapping rules apply:
- the upper left daughterboard (port 1) is mapped to span 2 of the PRI Gateway (MGC
IPE card slot 2 from a system software perspective)
- the upper right daughterboard (port 1) is mapped to span 4 of the PRI Gateway (MGC
IPE card slot 4 from a system software perspective)
- the lower left daughterboard (port 1) is mapped to span 6 of the PRI Gateway (MGC
IPE card slot 6 from a system software perspective)
- the lower right daughterboard (port 1) is mapped to span 8 of the PRI Gateway (MGC
IPE card slot 8 from a system software perspective)
• DPNSS/DASS protocols can also be implemented onboard (through a DCHI
daughterboard or onboard implementation). Onboard DPNSS/DASS interfaces (DCHI
software) can be defined and associated with up to eight E1 spans based on the following
mapping rule:
- DCHI software can be defined on any span (1, 2, 3, 4, 5, 6, 7, 8) on the PRI Gateway.
Each DCHI software span must be defined in the system software in the MGC IPE card
in the slot that is the same as the span number. For example, span 2 of the PRI Gateway
must be defined in MGC IPE card slot 2.
• The maximum usage for DCH interfaces in the PRI Gateway is:
- four spans for pure DCHI daughterboard configuration
- eight spans for pure onboard DCHI software configuration
Media Gateway 1000E PRI Gateway Installation and Commissioning
D-channel daughterboards
March 2013 43