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EZ-KIT Lite Hardware Reference
Figure 2-4. DIP Switch Locations and Default Settings
Positions 1 and 2 determine the clock routing for the audio oscillator to
the codec and to the processor.
Figure 2-5
illustrates how the switch posi-
tions 1 and 2 are connected on the board. In the default position, route
the
pin to
(in software) to clock the AD1835A.
DAI_P17
DAI_P6
Position 3 of the
switch determines if the AD1835A device is a master
SW7
or is a slave. If the AD1835A is a master, the device's serial interface gen-
erates the frame sync and clock signals necessary to transfer data. When
the device is a slave, the processor must generate the frame sync and clock
signals. By default, position 3 is "
", and the AD1835A generates the
ON
control signals.
ADSP-21364 EZ-KIT Lite Evaluation System Manual
2-9
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