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VisualDSP++ Interface
Table 1-6. Other Target Options
Option
Verify all writes to target
memory
Reset cycle counters on
run
hang to clear itself, such as when waiting for a host processor to read or
write data. In other cases, it is not possible to clear the core hang, and a
processor reset must occur to continue the debugging session.
Table 1-7
describes the EZ-KIT Lite's core hang operations.
Table 1-7. Core Hang Operations
Option
Abort
Retry
Ignore
Clear
Acknowledge
Reset
1-14
Description
Validates all memory writes to the processor. After each write, a read
is performed and the values are checked for a matching condition.
Enable this option during initial program development to locate
and fix initial build problems (such as attempting to load data into
non-existent memory).
Clear this option to increase performance while loading executable
files since VisualDSP++ does not perform the extra reads that are
required to verify each write.
Resets the cycle count registers to zero before a Run command is
issued. Select this option to count the number of cycles executed
between breakpoints in a program.
Description
Abort the hung operation. This causes the offending instruction to be
aborted in the pipeline.
Allows you to remedy the hung operation. For example, if a host proces-
sor is holding off the processor, you can cause the host to clear the hung
condition.
Performs a software reset on the target board.
Aborts the hung operation. This causes the offending instruction to be
aborted in the pipeline.
Allows you to remedy the hung operation. For example, if a host proces-
sor is holding off the processor, you can cause the host to clear the hung
condition.
Performs a software reset on the target board.
ADSP-21364 EZ-KIT Lite Evaluation System Manual
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