Table of Contents
Advertisement
System Architecture
To use the DAI for a different purpose, disable any signal driving the DAI
pins, with a switch. See
to. In addition, the codec setup switch allows flexible routing of the
12.288 MHz audio oscillator's output signal. By default, this signal is
used as the master clock (
All of the DAI signals are available externally via the expansion interface
connectors (
J3–1
these connectors can be found in
SPI Interface
The serial peripheral interconnect (SPI) interface of the processor con-
nects to an SPI flash memory and the AD1835A audio codec. The
pin is used as a memory select for accessing the SPI flash memory, and the
pin is used for accessing the AD1835A's configuration registers.
FLAG3
All of the SPI signals are available externally via the expansion interface
connectors (
J3–1
these connectors can be found in "Schematics" on page B-1.
FLAG Pins
The processor has four general-purpose IO
the connection of each flag.
Table 2-1. IO FLAG Pins
FLAG Pin
FLAG0
FLAG1
FLAG2
FLAG3
2-6
"Codec Setup Switch (SW7)" on page 2-8
) for the AD1835A codec.
MCLK
), as well as the 0.1' spaced header
"Schematics" on page
), as well as the 0.1' spaced header
EZ-KIT Lite Function
SPI flash chip select
Push button (
) input
SW1
Push button (
) input
SW2
AD1835A SPI interface chip select
ADSP-21364 EZ-KIT Lite Evaluation System Manual
. The pinout of
P3
B-1.
. The pinout of
P2
pins.
Table 2-1
FLAG
for how
FLAG0
describes
Advertisement
Table of Contents
