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Analog Audio
The master input clock (MCLK) for the AD1835A can be generated by
the on-board 12.288 MHz oscillator or can be supplied by one of the DAI
pins of the processor. Using one if the pins to generate the MCLK, as
opposed to the on-board oscillator, allows synchronization of multiple
devices in the system. This is done on the EZ-KIT Lite when data is com-
ing from the SPDIF receiver and being output through the audio codec.
The SPDIF MCLK is routed to the AD1835A MCLK in the processor's
SRU. It is also necessary to disable the on-board audio oscillator from
driving the audio codec and the processor's input pin. For instructions on
how to configure the clock, refer to
page
2-8.
The AD1835A codec can be configured as a master or as a slave, depend-
ing on DIP switch settings. In master mode, the AD1835A drives the
serial port clock and frame sync signals to the processor. In slave mode,
the processor must generate and drive all of the serial port clock and frame
sync signals. For information on how to set the mode, refer to
Setup Switch (SW7)" on page
The AD1835A audio codec's internal configuration registers are config-
ured using the SPI port of the processor. The
select for the device. For information on how to configure the multichan-
nel codec, refer to the codec datasheet, which can be found at
www.analog.com
The RCA connector (
electret microphone on this connector, configure the
the instructions in
page
2-8. The four output channels connect to the RCA connector
Channel 4 of the codec connects to the headphone jack
information about the connectors see
Example programs are included in the EZ-KIT Lite installation directory
to demonstrate how to configure and use the board's analog audio
interface.
1-8
2-8.
.
) is used to input analog audio. When using an
J4
"Electret Microphone Select Switch (SW6)" on
ADSP-21364 EZ-KIT Lite Evaluation System Manual
"Codec Setup Switch (SW7)" on
register is used as the
FLAG3
SW6
"Connectors" on page
"Codec
switch according
.
J5
. For more
J6
2-15.
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