Pci Express Gen 2 Settings - Congatec COM Express conga-TCA3 User Manual

10.4.24

PCI Express GEN 2 Settings

Feature
Completion Timeout
ARI Forwarding
AtomicOp Requester Enable
AtomicOp Egress Blocking
IDO Request Enable
IDO Completion Enable
LTR Mechanism Enable
End-End TLP Prefix Blocking
Target Link Speed
Clock Power Management
Compliance SOS
Hardware Autonomous Width
Hardware Autonomous Speed
Note
Ensure that the hardware supports the feature(s) described in this table if you want to use them. Features listed in this table but not supported
by the hardware cannot be used.
Copyright © 2014 congatec AG
Options Description
Default Select the completion timeout value:
Shorter 'Default' - 50us to 50ms.
Longer 'Shorter' - Software will use shorter timeout ranges.
Disabled 'Longer' - Software will use longer timeout ranges.
Disabled If set to 'Enabled', the downstream port disables it's traditional device number field when
Enabled turning a type 1 configuration request into a type 0 configuration request, permitting
access to extended functions in an ARI device immediately below the port.
Disabled
If set to 'Enabled', this feature initiates AtomicOp requests only if bus master enable bit is
Enabled in the command register set.
Disabled
If set to 'Enabled', outbound AtomicOp requests via egress ports will be blocked.
Enabled
Disabled If set to 'Enabled', this feature permits setting the number of ID-Based Ordering (IDO) bit
Enabled (Attribute[2]) requests to be initiated.
Disabled If set to 'Enabled', this feature permits setting the number of ID-Based Ordering (IDO) bit
Enabled (Attribute[2]) requests to be initiated.
Disabled Enable or disable the Latency Tolerance Reporting (LTR) mechanism.
Enabled
Disabled If set to 'Enabled', this function will block forwarding of TLPs containing End-End TLP
Enabled prefixes.
Auto Select the target link speed:
Force to 2.5 GT/s 'Auto' - Uses HW initialized data.
Force to 5.0 GT/s 'Force to X.X GT/s' - Sets an upper limit on link operational speed by restricting the values
advertised by the upstream component in its training sequences.
Disabled
If set to 'Enabled', the device is permitted to use CLKREQ# signal for power management
Enabled of link clock in accordance to protocol as defined in appropriate form factor specification.
Disabled If set to 'Enabled', this feature forces LTSSM to send SKP ordered sets between
Enabled sequences when sending a compliance pattern or a modified compliance pattern.
Enabled If set to 'Disabled', this feature disables the hardware´s ability to change link width, except
Disabled
for the purpose of correcting unstable link operation.
Enabled If set to 'Disabled', this feature disables the hardware´s ability to change link speed,
Disabled
except speed rate reduction for the purpose of correcting unstable link operation.
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