Spi Interfaces - Quectel QuecOpen AG521R-NA Hardware Design

3.14. SPI Interfaces

The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of SPI is up
to 50 MHz.
Table 20: Pin Definition of SPI Interfaces
Pin Name Pin No.
SPI1_CLK 216
SPI1_CS 213
SPI1_MISO 219
SPI1_MOSI 210
The following figure shows the timing relationship of SPI interfaces. The related parameters of SPI timing are
shown in the table below.
Table 21: Parameters of SPI Interface Timing
Parameter Description
T SPI clock period
t(ch) SPI clock high-level time
AG521R-NA_QuecOpen_Hardware_Design
I/O Description
DO SPI1 clock
DO SPI1 chip select
DI SPI1 master-in salve-out
DO SPI1 master-out slave-in
T
SPI_CS
1
SPI_CLK
MSB
SPI_MOSI
t(mov)
SPI_MISO
Figure 26: SPI Timing
AG521R-NA QuecOpen Hardware Design
Comment
1.8 V power domain.
Can be configured to GPIO.
If unused, keep them open.
t(ch) t(cl)
4
2 3
t(mis)
t(mih)
Min. Typ.
20.0 -
9.0 -
Automotive Module Series
Max. Unit
- ns
- ns
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