Display Port; Real-Time Clock (Rtc); Usb 3.0 Implementation Example - Enclustra Mars XU3 User Manual

Details on the built-in USB 2.0/3.0 controller and on the usage of the PS GTR lanes are available in the Zynq
UltraScale+ MPSoC Technical Reference Manual [19] and in the Zynq UltraScale+ MPSoC Overview [23].
Figure 10 shows an example of a USB 3.0 implementation using the built-in Xilinx USB 3.0 interface and the
USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board.
Figure 10: USB 3.0 Implementation Example
2.22

Display Port

Xilinx Zynq Ultrascale+ devices feature two built-in DisplayPort controllers and PHYs, supporting up to two
lanes at a 5.4 Gbit/sec line rate. Each lane is represented by one of the PS GTR lines, available on the module
connector.
Warning!
The maximum bandwidth of the GTR transceivers on the Mars XU3 SoC module is limited to 5 Gbit/sec
by the module connector. For DisplayPort implementation, a link rate of 2.7 Gbit/sec per lane may be
used.
A 27 MHz differential clock is available on the module and connected to PS_MGTREFCLK3 pins, to be used
as a reference clock for the DisplayPort interface. It is also possible to provide another reference clock from
the base board to the MGTPS_REFCLK* pins.
Details on the built-in DisplayPort controller and on the usage of the PS GTR lanes is available in the Zynq
UltraScale+ MPSoC Technical Reference Manual [19] and in the Zynq UltraScale+ MPSoC Overview [23].
2.23

Real-Time Clock (RTC)

Zynq Ultrascale+ devices include an internal real-time clock. The internal RTC can be accessed by the plat-
form management unit (PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC
Technical Reference Manual [19].
The RTC crystal pad input and crystal pad output are connected on the Mars XU3 SoC module to a 32.768
kHz oscillator.
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