Display Port; Real-Time Clock (Rtc); Usb 3.0 Implementation Example - Enclustra Andromeda XZU90 User Manual

A 100 MHz differential clock is available on the module and connected to PS_MGTREFCLK2 pins, to be
used as a reference clock for the USB 3.0 interface. It is also possible to provide another reference clock
from the base board to the MGTPS_REFCLK* pins.
Details on the built-in USB 2.0/3.0 controller and on the usage of the PS GTR lanes are available in the
Zynq UltraScale+ MPSoC Technical Reference Manual [15] and in the Zynq UltraScale+ MPSoC Overview
[19].
Figure 11 shows an example of a USB 3.0 implementation using the built-in Xilinx USB 3.0 interface and
the USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board.
Figure 11: USB 3.0 Implementation Example
2.22

Display Port

Xilinx Zynq UltraScale+ devices feature a built-in DisplayPort controller and PHY, supporting up to two
lanes at a 5.4 Gbit/s line rate. Each lane is represented by one of the PS GTR lines, available on the module
connector.
A 27 MHz differential clock is available on the module and connected to PS_MGTREFCLK3 pins, to be
used as a reference clock for the DisplayPort interface. It is also possible to provide another reference
clock from the base board to the MGTPS_REFCLK* pins.
For the DisplayPort AUX port, MIO pins 34-37 are available on the module connector and can be used
on the baseboard for DP implementation.
Details on the built-in DisplayPort controller and on the usage of the PS GTR lanes is available in the Zynq
UltraScale+ MPSoC Technical Reference Manual [15] and in the Zynq UltraScale+ MPSoC Overview [19].
2.23

Real-Time Clock (RTC)

Zynq UltraScale+ devices include an internal real-time clock. More information on the RTC is available in
the Zynq UltraScale+ MPSoC Technical Reference Manual [15].
The RTC crystal pad input and crystal pad output are connected on the Andromeda XZU90 module to a
32.768 kHz oscillator.
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