Module Description; Block Diagram; Hardware Block Diagram - Enclustra Mars XU3 User Manual

2 Module Description

2.1

Block Diagram

Figure 1: Hardware Block Diagram
The main component of the Mars XU3 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of
its I/O pins are connected to the Mars module connector, making 88 regular user I/Os available to the user.
Further, four MGT GTR pairs are available on the module connector, making possible the implementation of
several high-speed protocols such as PCIe Gen2 4 and USB 3.0 (simultaneous usage of all the interfaces
is limited to the available hardware resources i.e. number of transceivers and lane mapping).
The MPSoC device can boot from the on-board QSPI flash, from the eMMC flash or from an external SD
card. For development purposes, a JTAG interface is connected to Mars module connector.
The available standard configurations include a 16 GB eMMC flash, a 64 MB quad SPI flash and 1 GB or 2 GB
DDR4 SDRAM.
Further, the module is equipped with a Gigabit Ethernet PHY and a USB 2.0 OTG PHY, making it ideal for
communication applications.
A real-time clock is available on the Xilinx Zynq Ultrascale+ MPSoC device.
On-board clock generation is based on a 33.33 MHz crystal oscillator. In addition, two oscillators delivering
100 MHz and 27 MHz reference clocks for the MGT GTR lines, are equipped on the module.
The module can be operated using a 3.3 V DC input, from which all necessary supply voltages are generated.
Some of these voltages are available on the Mars module connector to supply circuits on the base board,
or can be used as voltage inputs for the FPGA banks.
Four LEDs are connected to the MPSoC pins for status signaling.
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